LTC2242IUP-12#PBF Datasheet LTC2242IUP-12#PBF, LTC2242CUP-12#PBF, LTC2242IUP-12#TRPBF | P19-P21

LTC2242-12

224212fc

APPLICATIONS INFORMATION

Maximum and Minimum Encode Rates

The maximum encode rate for the LTC2242-12 is 250Msps.

For the ADC to operate properly, the encode signal should

have a 50% (±5%) duty cycle. Each half cycle must have

at least 1.9ns for the ADC internal circuitry to have enough

settling time for proper operation. Achieving a precise 50%

duty cycle is easy with differential sinusoidal drive using

a transformer or using symmetric differential logic such

as PECL or LVDS.

An optional clock duty cycle stabilizer circuit can be used if

the input clock has a non 50% duty cycle. This circuit uses

the rising edge of the ENC

pin to sample the analog input.

The falling edge of ENC

is ignored and the internal falling

edge is generated by a phase-locked loop. The input clock

duty cycle can vary from 40% to 60% and the clock duty

cycle stabilizer will maintain a constant 50% internal duty

cycle. If the clock is turned off for a long period of time,

the duty cycle stabilizer circuit will require one hundred

clock cycles for the PLL to lock onto the input clock. To

use the clock duty cycle stabilizer, the MODE pin should be

connected to 1/3V

or 2/3V

using external resistors.

The lower limit of the LTC2242-12 sample rate is determined

by droop of the sample-and-hold circuits. The pipelined

architecture of this ADC relies on storing analog signals on

small valued capacitors. Junction leakage will discharge

the capacitors. The speciﬁ ed minimum operating frequency

for the LTC2242-12 is 1Msps.

DIGITAL OUTPUTS

Table 1 shows the relationship between the analog input

voltage, the digital data bits, and the overﬂ ow bit.

Figure 11. Transformer Driven ENC

/ENC

–

Figure 12a. Single-Ended ENC Drive,

Not Recommended for Low Jitter

Figure 12b. ENC Drive Using LVDS

LTC2242-12

224212 F11

ENC

–

ENC

1.5V BIAS

0.1μF

MA/COM

ETC1-1-13

CLOCK

INPUT

100Ω8.2pF

0.1μF

50Ω

••

50Ω

4.8k

TO INTERNAL

ADC CIRCUITS

224212 F12a

ENC

–

1.5V

THRESHOLD

= 1.5V

ENC

0.1μF

LTC2242-12

224212 F12b

ENC

–

ENC

LVDS

CLOCK

100Ω

0.1μF

LTC2242-12

0.1μF

LTC2242-12

224212fc

APPLICATIONS INFORMATION

Table 1. Output Codes vs Input Voltage

– A

–

(2V Range) OF

D11 – D0

(Offset Binary)

D11 – D0

(2’s Complement)

>+1.000000V

+0.999512V

+0.999024V

1111 1111 1111

1111 1111 1110

0111 1111 1111

0111 1111 1110

+0.000488V

0.000000V

–0.000488V

–0.000976V

1000 0000 0001

1000 0000 0000

0111 1111 1111

0111 1111 1110

0000 0000 0001

0000 0000 0000

1111 1111 1111

1111 1111 1110

–0.999512V

–1.000000V

<–1.000000V

0000 0000 0001

0000 0000 0000

1000 0000 0001

1000 0000 0000

Digital Output Modes

The LTC2242-12 can operate in several digital output

modes: LVDS, CMOS running at full speed, and CMOS

demultiplexed onto two buses, each of which runs at half

speed. In the demultiplexed CMOS modes the two buses

(referred to as bus A and bus B) can either be updated on

alternate clock cycles (interleaved mode) or simultaneously

(simultaneous mode). For details on the clock timing, refer

to the timing diagrams.

The LVDS pin selects which digital output mode the part

uses. This pin has a four-level logic input which should

be connected to GND, 1/3V

, 2/3V

or V

. An external

resistor divider can be used to set the 1/3V

or 2/3V

logic values. Table 2 shows the logic states for the LVDS

pin.

Table 2. LVDS Pin Function

LVDS DIGITAL OUTPUT MODE

GND Full-Rate CMOS

1/3V

Demultiplexed CMOS, Simultaneous Update

2/3V

Demultiplexed CMOS, Interleaved Update

LVDS

Digital Output Buffers (CMOS Modes)

Figure 13a shows an equivalent circuit for a single

output buffer in the CMOS output mode. Each buffer is

and OGND, which are isolated from the

ADC power and ground. The additional N-channel transistor

in the output driver allows operation down to voltages as

low as 0.5V. The internal resistor in series with the output

makes the output appear as 50Ω to external circuitry and

may eliminate the need for external damping resistors.

As with all high speed/high resolution converters, the

digital output loading can affect the performance. The

digital outputs of the LTC2242-12 should drive a minimal

capacitive load to avoid possible interaction between the

digital outputs and sensitive input circuitry. The output

should be buffered with a device such as an 74VCX245

CMOS latch. For full speed operation the capacitive load

should be kept under 10pF.

Lower OV

voltages will also help reduce interference

from the digital outputs.

Digital Output Buffers (LVDS Mode)

Figure 13b shows an equivalent circuit for a differential

output pair in the LVDS output mode. A 3.5mA current is

steered from OUT

to OUT

–

or vice versa which creates a

±350mV differential voltage across the 100Ω termination

resistor at the LVDS receiver. A feedback loop regulates

the common mode output voltage to 1.25V. For proper

operation each LVDS output pair needs an external 100Ω

termination resistor, even if the signal is not used (such

as OF

/OF

–

or CLKOUT

/CLKOUT

–

). To minimize noise

the PC board traces for each LVDS output pair should be

routed close together. To minimize clock skew all LVDS PC

board traces should have about the same length.

LTC2242-12

224212fc

APPLICATIONS INFORMATION

Data Format

The LTC2242-12 parallel digital output can be selected

for offset binary or 2’s complement format. The format

is selected with the MODE pin. Connecting MODE to GND

or 1/3V

selects offset binary output format. Connecting

MODE to 2/3V

or V

selects 2’s complement output

format. An external resistor divider can be used to set the

1/3V

or 2/3V

logic values. Table 3 shows the logic

states for the MODE pin.

Table 3. MODE Pin Function

MODE PIN OUTPUT FORMAT

CLOCK DUTY

CYCLE STABILIZER

0 Offset Binary Off

1/3V

Offset Binary On

2/3V

2’s Complement On

2’s Complement Off

Overﬂ ow Bit

An overﬂ ow output bit indicates when the converter is

overranged or underranged. In CMOS mode, a logic high

on the OFA pin indicates an overﬂ ow or underﬂ ow on the

A data bus, while a logic high on the OFB pin indicates an

overﬂ ow or underﬂ ow on the B data bus. In LVDS mode,

a differential logic high on the OF

/OF

–

pins indicates an

overﬂ ow or underﬂ ow.

Output Clock

The ADC has a delayed version of the ENC

input available

as a digital output, CLKOUT. The CLKOUT pin can be used

Figure 13b. Digital Output in LVDS Mode

Figure 13a. Digital Output Buffer in CMOS Mode

to synchronize the converter data to the digital system.

This is necessary when using a sinusoidal encode. In

all CMOS modes, A bus data will be updated just after

CLKOUTA rises and can be latched on the falling edge of

CLKOUTA. In demux CMOS mode with interleaved update,

B bus data will be updated just after CLKOUTB rises and

can be latched on the falling edge of CLKOUTB. In demux

CMOS mode with simultaneous update, B bus data will be

updated just after CLKOUTB falls and can be latched on

the rising edge of CLKOUTB. In LVDS mode, data will be

updated just after CLKOUT

/CLKOUT

–

rises and can be

latched on the falling edge of CLKOUT

/CLKOUT

–

Output Driver Power

Separate output power and ground pins allow the output

drivers to be isolated from the analog circuitry. The power

supply for the digital output buffers, OV

, should be tied

to the same power supply as for the logic being driven.

For example if the converter is driving a DSP powered

by a 1.8V supply then OV

should be tied to that same

1.8V supply.

In the CMOS output mode, OV

can be powered with

any voltage up to 2.625V. OGND can be powered with any

voltage from GND up to 1V and must be less than OV

The logic outputs will swing between OGND and OV

In the LVDS output mode, OV

should be connected to a

2.5V supply and OGND should be connected to GND.

LTC2242-12

2242 F13a

0.1μF

43Ω

TYPICAL

DATA

OUTPUT

OGND

0.5V

TO 2.625V

PREDRIVER

LOGIC

DATA

FROM

LATCH

LTC2242-12

224212 F13b

LVDS

RECEIVER

OGND

1.25V

OUT

0.1μF

2.5V

OUT

–

100Ω

–

3.5mA

10k 10k

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LTC2242IUP-12#PBF

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 12-B, 250Msps ADC

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LTC2242IUP-12#PBF

LTC2242IUP-12#PBF

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