SL28PCIe10
.....................................Document #: Rev 1.1 Page 10 of 16
Absolute Maximum Conditions
Parameter Description Condition Min. Max. Unit
V
DD_3.3V
Main Supply Voltage 4.6 V
V
DD_IO
IO Supply Voltage 4.6 V
V
IN
Input Voltage Relative to V
SS
–0.5 4.6 V
DC
T
S
Temperature, Storage Non-functional –65 150 °C
T
A
Temperature, Operating
Ambient
Functional -40 85 °C
T
J
Temperature, Junction Functional 150 °C
Ø
JC
Dissipation, Junction to Case MIL-STD-883E Method 1012.1 20 °C/
W
Ø
JA
Dissipation, Junction to Ambient JEDEC (JESD 51) 60 °C/
W
ESD
HBM
ESD Protection (Human Body
Model)
MIL-STD-883, Method 3015 2000 V
UL-94 Flammability Rating At 1/8 in. V–0
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter Description Condition Min. Max. Unit
VDD core 3.3V Operating Voltage 3.3 ± 5% 3.135 3.465 V
V
IH
3.3V Input High Voltage (SE) 2.0 V
DD
+ 0.3 V
V
IL
3.3V Input Low Voltage (SE) V
SS
– 0.3 0.8 V
V
IHI2C
Input High Voltage SDATA, SCLK 2.2 V
V
ILI2C
Input Low Voltage SDATA, SCLK 1.0 V
V
IH_FS
FS Input High Voltage 0.7 VDD+0.3 V
V
IL_FS
FS Input Low Voltage V
SS
– 0.3 0.35 V
I
IH
Input High Leakage Current Except internal pull-down resistors, 0 < V
IN
< V
DD
–5A
I
IL
Input Low Leakage Current Except internal pull-up resistors, 0 < V
IN
< V
DD
–5 A
V
OH
3.3V Output High Voltage (SE) I
OH
= –1 mA 2.4 V
V
OL
3.3V Output Low Voltage (SE) I
OL
= 1 mA 0.4 V
V
DD IO
Low Voltage IO Supply Voltage 1 3.465 V
I
OZ
High-impedance Output
Current
–10 10 A
C
IN
Input Pin Capacitance 1.5 5 pF
C
OUT
Output Pin Capacitance 6pF
L
IN
Pin Inductance 7 nH
IDD_
PD
Power Down Current 1 mA
I
DD_3.3V
Dynamic Supply Current All outputs enabled. SE clocks with 8” traces and
4pF load. Differential clocks with 7” traces and
2pF load.
–65mA
I
DD_VDD_IO
Dynamic Supply Current All outputs enabled. SE clocks with 8” traces and
4pF load. Differential clocks with 7” traces and
2pF load.
–25mA
SL28PCIe10
.....................................Document #: Rev 1.1 Page 11 of 16
AC Electrical Specifications
Parameter Description Condition Min. Max. Unit
Crystal
L
ACC
Long-term Accuracy Measured at VDD/2 differential 250 ppm
Clock Input
T
DC
CLKIN Duty Cycle Measured at VDD/2 47 53 %
T
R
/T
F
CLKIN Rise and Fall Times Measured between 0.2V
DD
and 0.8V
DD
0.5 4.0 V/ns
T
CCJ
CLKIN Cycle to Cycle Jitter Measured at VDD/2 250 ps
T
LTJ
CLKIN Long Term Jitter Measured at VDD/2 350 ps
V
IH
Input High Voltage XIN / CLKIN pin 2 VDD+0.3 V
V
IL
Input Low Voltage XIN / CLKIN pin 0.8 V
I
IH
Input High Current XIN / CLKIN pin, VIN = VDD 35 uA
I
IL
Input Low Current XIN / CLKIN pin, 0 < VIN <0.8 -35 uA
SRC at 0.7V
T
DC
SRC Duty Cycle Measured at 0V differential 45 55 %
T
PERIOD
100 MHz SRC Period Measured at 0V differential at 0.1s
9.99900 10.0010
ns
T
PERIODSS
100 MHz SRC Period, SSC Measured at 0V differential at 0.1s
10.02406 10.02607
ns
T
PERIODAbs
100 MHz SRC Absolute Period Measured at 0V differential at 1 clock
9.87400 10.1260
ns
T
PERIODSSAbs
100 MHz SRC Absolute Period, SSC Measured at 0V differential at 1 clock
9.87406 10.1762
ns
T
SKEW(window)
Any SRC Clock Skew from the earliest
bank to the latest bank
Measured at 0V differential 3.0 ns
T
CCJ
SRC Cycle to Cycle Jitter Measured at 0V differential 125 ps
RMS
GEN1
Output PCIe* Gen1 REFCLK phase
jitter
BER = 1E-12 (including PLL BW 8 - 16
MHz, ζ = 0.54, Td=10 ns,
Ftrk=1.5 MHz)
0108ps
RMS
GEN2
Output PCIe* Gen2 REFCLK phase
jitter
Includes PLL BW 8 - 16 MHz, Jitter
Peaking = 3dB, ζ = 0.54, Td=10 ns),
Low Band, F < 1.5MHz
03.0ps
RMS
GEN2
Output PCIe* Gen2 REFCLK phase
jitter
Includes PLL BW 8 - 16 MHz, Jitter
Peaking = 3dB, ζ = 0.54, Td=10 ns),
Low Band, F < 1.5MHz
03.1ps
L
ACC
SRC Long Term Accuracy Measured at 0V differential 100 ppm
T
R
/ T
F
SRC Rising/Falling Slew Rate Measured differentially from ±150 mV 2.5 8 V/ns
T
RFM
Rise/Fall Matching Measured single-endedly from ±75 mV 20 %
V
HIGH
Voltage High 1.15 V
V
LOW
Voltage Low –0.3 V
V
OX
Crossing Point Voltage at 0.7V Swing 300 550 mV
27M_NSS at 3.3V
T
DC
Duty Cycle Measurement at 1.5V 45 55 %
T
PERIOD
Spread 27M Period Measurement at 1.5V 37.03594 37.03813 ns
T
R
/ T
F
Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns
T
CCJ
Cycle to Cycle Jitter Measurement at 1.5V 300 ps
L
ACC
27_M Long Term Accuracy Measured at crossing point V
OX
–50ppm
REF
T
DC
REF Duty Cycle Measurement at 1.5V 45 55 %
SL28PCIe10
.....................................Document #: Rev 1.1 Page 12 of 16
Test and Measurement Setup
For Reference Clock
The following diagram shows the test load configurations for the single-ended REF output signal.
T
PERIOD
REF Period
Measurement at 1.5V 39.996 40.004 ns
T
R
/ T
F
REF Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns
T
CCJ
REF Cycle to Cycle Jitter Measurement at 1.5V 500 ps
L
ACC
Long Term Accuracy Measurement at 1.5V 50 ppm
ENABLE/DISABLE and SET-UP
T
STABLE
Clock Stabilization from Power-up 1.8 ms
T
SS
Stopclock Set-up Time 10.0 ns
AC Electrical Specifications (continued)
Parameter Description Condition Min. Max. Unit

SL28PCIe10ALI

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products PCIe clk G., Xin(14M or 25M)-->4 PCIe out (gen2),refout,48M,27M, prog.out
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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