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SL28PCIE10ALIT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
SL28PCIe10
.......................................Document #: Rev 1.1 Page 4 of 16
.... Stop
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol Byte Read Protocol
Bit Description Bit Description
1Start 1Start
8:2 Slave address–7 bits 8:2 Slave address–7 bits
9Write 9Write
10 Acknowledge from slave 10 Acknowledge from slave
18:11 Command Code–8 bits 18:11 Command Code–8 bits
19 Acknowledge from slave 19 Acknowledge from slave
27:20 Data byte–8 bits 20 Repeated start
28 Acknowledge from slave 27:21 Slave address–7 bits
29 Stop 28 Read
29 Acknowledge from slave
37:30 Data from slave–8 bits
38 NOT Acknowledge
39 Stop
Table 2. Block Read and Block Write Protocol (continued)
Block Write Protocol Block Read Protocol
Bit Description Bit Description
SL28PCIe10
.......................................Document #: Rev 1.1 Page 5 of 16
Control Registers
Byte 0: Control Register 0
Bit @Pup Name Description
7 HW RESERVED RESERVED
6 0 RESERVED RESERVED
5 1 RESERVED RESERVED
4 0 RESERVED RESERVED
3 0 RESERVED RESERVED
2 0 RESERVED RESERVED
1 0 RESERVED RESERVED
0 1 PD_Restore Save configuration when PD# is asserted
0 = Config. cleared, 1 = Config. saved
Byte 1: Control Register 1
Bit @Pup Name Description
7 1 RESERVED RESERVED
6 0 PLL1_SS_DC Select for down or center SS
0 = Down spread, 1 = Center spread
5 0 RESERVED RESERVED
4 0 RESERVED RESERVED
3 0 RESERVED RESERVED
2 1 RESERVED RESERVED
1 0 RESERVED RESERVED
0 1 RESERVED RESERVED
Byte 2: Control Register 2
Bit @Pup Name Description
7 1 REF_OE Output enable for REF
0 = Output Disabled, 1 = Output Enabled
6 1 RESERVED RESERVED
5 1 RESERVED RESERVED
4 1 RESERVED RESERVED
3 1 RESERVED RESERVED
2 1 RESERVED RESERVED
1 1 RESERVED RESERVED
0 1 RESERVED RESERVED
Byte 3: Control Register 3
Bit @Pup Name Description
7 1 RESERVED RESERVED
6 1 RESERVED RESERVED
5 1 RESERVED RESERVED
4 1 RESERVED RESERVED
3 1 RESERVED RESERVED
2 1 RESERVED RESERVED
1 1 RESERVED RESERVED
SL28PCIe10
.......................................Document #: Rev 1.1 Page 6 of 16
0 1 RESERVED RESERVED
Byte 3: Control Register 3
Byte 4: Control Register 4
Bit @Pup Name Description
7 1 RESERVED RESERVED
6 1 SRC0_OE Output enable for SRC0
0 = Output Disabled, 1 = Output Enabled
5 1 SRC1_OE Output enable for SRC1
0 = Output Disabled, 1 = Output Enabled
4 1 RESERVED RESERVED
3 1 SRC3_OE Output enable for SRC3
0 = Output Disabled, 1 = Output Enabled
2 1 SRC2_OE Output enable for SRC2
0 = Output Disabled, 1 = Output Enabled
1 1 PLL1_SS_EN Enable PLL1s spread modulation,
0 = Spread Disabled, 1 = Spread Enabled
0 1 RESERVED RESERVED
Byte 5: Control Register 5
Bit @Pup Name Description
7 0 RESERVED RESERVED
6 0 RESERVED RESERVED
5 0 RESERVED RESERVED
4 0 RESERVED RESERVED
3 0 RESERVED RESERVED
2 0 RESERVED RESERVED
1 0 RESERVED RESERVED
0 0 RESERVED RESERVED
Byte 6: Control Register 6
Bit @Pup Name Description
7 0 RESERVED RESERVED
6 0 RESERVED RESERVED
5 0 REF Bit1 REF slew rate control
(see Byte 13 for Slew Rate Bit 0 and Bit 2)
0 = High, 1 = Low
4 0 RESERVED RESERVED
3 0 27MHz Bit 1 27MHz slew rate control
(see Byte 13 for Slew Rate Bit 0 and Bit 2)
0 = High, 1 = Low
2 0 RESERVED RESERVED
1 0 RESERVED RESERVED
0 0 RESERVED RESERVED
Byte 7: Vendor ID
Bit @Pup Name Description
7 0 Rev Code Bit 3 Revision Code Bit 3
6 1 Rev Code Bit 2 Revision Code Bit 2
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

SL28PCIE10ALIT

Mfr. #:
Buy SL28PCIE10ALIT
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products ClkGen Xin-4PCIE out G2 R-ot 48M 27M Pgot
Lifecycle:
New from this manufacturer.
Delivery:
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