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LT3695HMSE#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
LT3695 Series
10
3695fa
BLOCK DIAGRAM
V
IN
V
IN
V
OUT
C1
R
T
PG
RUN/SS
SYNC
RT
+
–
INTERNAL 0.8V REF
11
+
–
SOFT-START
0.720V
ERROR AMP
OSCILLATOR
250kHz TO 2.2MHz
DISABLE
SYNC
OUT
OUTB
+
–
+
–
Burst Mode
DETECT
THERMAL
SHUTDOWN
V
C
CLAMP
2
4
15
16
9
5
7
13
8
6
R1R2
FBGND
OVLO
SLOPE COMP
R
S
Q
DA
PGND
SW
BOOST
BD
V
C
C
C
C3
L1
D1
C2
C
F
R
C
3695 BDa
1
PGND
17
14
V
IN
V
IN
V
OUT
C1
R
T
PG
RUN/SS
SYNC
RT
+
–
INTERNAL 0.8V REF
+
–
SOFT-START
0.720V
ERROR AMP
OSCILLATOR
250kHz TO 2.2MHz
DISABLE
SYNC
OUT
OUTB
+
–
+
–
Burst Mode
DETECT
THERMAL
SHUTDOWN
V
C
CLAMP
2
4
14
16
9
5
7
11
8
6
R1R2
GND
OVLO
SLOPE COMP
R
S
Q
DA
PGND
SW
BOOST
OUT1
13
OUT2
V
C
C
C
C3
L1
D1
C2
C
F
R
C
3695 BD
1
PGND
17
12
LT3695-3.3/LT3695-5
LT3695
LT3695 Series
11
3695fa
OPERATION
The LT3695 series are constant-frequency, current mode
step-down regulators. An oscillator, with frequency set by
R
T
, enables an RS fl ip-fl op, turning on the internal power
switch. An amplifi er and comparator monitor the current
fl owing between the V
IN
and SW pins, turning the switch
off when this current reaches a level determined by the
voltage at V
C
. An error amplifi er measures the output
voltage through an external resistor divider tied to the FB
pin (LT3695) or through an internal resistor divider con-
nected to the output voltage (LT3695-3.3, LT3695-5), and
servos the V
C
pin. If the error amplifi er’s output increases,
more current is delivered to the output; if it decreases,
less current is delivered. An active clamp on the V
C
pin
provides current limit. The V
C
pin is also clamped to the
voltage on the RUN/SS pin; soft-start is implemented by
generating a voltage ramp at the RUN/SS pin using an
external resistor and capacitor.
An internal regulator provides power to the control circuitry.
The bias regulator normally draws power from the V
IN
pin,
but if the BD pin is connected to an external voltage higher
than 3V (LT3695) or if the output voltage connected to the
OUT 1 and OUT2 pins exceeds 3V (LT3695-3.3, LT3695-5),
bias power will be drawn from the external source. This
improves effi ciency. The RUN/SS pin is used to place the
LT3695 regulators in shutdown, disconnecting the output
and reducing the input current to less than 1µA.
The switch driver operates from either the input or from
the BOOST pin. An external capacitor and the internal boost
diode are used to generate a voltage at the BOOST pin that
is higher than the input supply. This allows the driver to
fully saturate the internal bipolar NPN power switch for
effi cient operation.
To further optimize effi ciency, the LT3695 regulators au-
tomatically switch to Burst Mode operation in light load
situations. Between bursts, all circuitry associated with
controlling the output switch is shut down, reducing the
input supply current to 75µA in a typical application.
The oscillator reduces the LT3695 regulators’ operating
frequency when the voltage at the FB pin (LT3695) or the
OUT1,2 pins (LT3695-3.3, LT3695-5) is low. This frequency
foldback helps to control the output current during start-up
and overload conditions.
Internal circuitry monitors the current fl owing through the
catch diode via the DA pin and delays the generation of
new switch pulses if this current is too high (above 1.6A
nominal). This mechanism also protects the part during
short-circuit and overload conditions by keeping the cur-
rent through the inductor under control.
The LT3695 regulators contain a power good comparator
which trips when the FB pin (LT3695) or the OUT1,2 pins
(LT3695-3.3, LT3695-5) are at 90% of their regulated
value. The PG output is an open-collector transistor that
is off when the output is in regulation, allowing an external
resistor to pull the PG pin high. Power good is valid when
the LT3695 regulators are enabled and V
IN
is above the
minimum input voltage.
The LT3695 regulators have an overvoltage protection fea-
ture which disables switching action when V
IN
goes above
38V (typical) during transients. The LT3695 regulators can
then safely sustain transient input voltages up to 60V.
LT3695 Series
12
3695fa
APPLICATIONS INFORMATION
FB Resistor Network (LT3695)
The output voltage of the LT3695 is programmed with a
resistor divider between the output and the FB pin. Choose
the resistor values according to:
RR
V
V
OUT
12
08
1= −
⎛
⎝
⎜
⎞
⎠
⎟
.
Reference designators refer to the Block Diagram of the
LT3695. 1% resistors are recommended to maintain output
voltage accuracy.
Setting the Switching Frequency
The LT3695 regulators use a constant-frequency PWM
architecture that can be programmed to switch from
250kHz to 2.2MHz by using a resistor tied from the RT
pin to ground. A table showing the necessary R
T
value for
a desired switching frequency is in Table 1.
Table 1. Switching Frequency vs R
T
Value
SWITCHING FREQUENCY (MHz) R
T
VALUE (kΩ)
0.25 158
0.3 127
0.4 90.9
0.5 71.5
0.6 57.6
0.7 47.5
0.8 40.2
0.9 34
1.0 29.4
1.2 22.6
1.4 18.2
1.6 14.7
1.8 12.1
2.0 9.76
2.2 8.06
Operating Frequency Trade-Offs
Selection of the operating frequency is a trade-off between
effi ciency, component size, minimum dropout voltage and
maximum input voltage. The advantage of high frequency
operation is that smaller inductor and capacitor values may
be used. The disadvantages are lower effi ciency, lower
maximum input voltage and higher dropout voltage. The
highest acceptable switching frequency (f
SW(MAX)
) for a
given application can be calculated as follows:
f
VV
tVVV
SW MAX
OUT D
ON MIN IN SW D
()
()
()
=
+
− +
where V
IN
is the typical input voltage, V
OUT
is the output
voltage, V
D
is the catch diode drop (~0.5V) and V
SW
is the
internal switch drop (~0.5V at max load). This equation
shows that lower switching frequency is necessary to
safely accommodate high V
IN
/V
OUT
ratio. Also, as shown
in the Input Voltage Range section, lower frequency allows
a lower dropout voltage. Input voltage range depends on
the switching frequency because the LT3695 regulators’
switch has fi nite minimum on and off times. An internal
timer forces the switch to be off for at least t
OFF(MIN)
per
cycle; this timer has a maximum value of 210ns (250ns
for T
J
> 125°C). On the other hand, delays associated with
turning off the power switch dictate the minimum on-time,
t
ON(MIN)
, before the switch can be turned off; t
ON(MIN)
has a
maximum value of 150ns over temperature. The minimum
and maximum duty cycles that can be achieved taking
minimum on and off times into account are:
DC
MIN
= f
SW
t
ON(MIN)
DC
MAX
= 1 – f
SW
t
OFF(MIN)
where f
SW
is the switching frequency, t
ON(MIN)
is the
minimum switch on time (150ns), and t
OFF(MIN)
is the
minimum switch off time (210ns, 250ns for T
J
> 125°C).
These equations show that the duty cycle range increases
when the switching frequency is decreased.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

LT3695HMSE#PBF

Mfr. #:
Buy LT3695HMSE#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 36V (60V Transient), 1A (Iout) MicroPower 2.2MHz Step-Down Switching Regulator with 1A Fault Protection in MSOP-16E
Lifecycle:
New from this manufacturer.
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