MAX9491
Factory Programmable Single PLL
Clock Generator
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should be less than 10pF, including board parasitic
capacitance. To achieve up to ±200ppm pullability, make
sure the crystal-loading capacitance is less than 14pF.
The VCXO is a free-running oscillator. It starts oscillating
with an internal POR signal and can be disabled by PD.
When VCXO is not used, connect TUNE to V
DD
.
Applications Information
Using an Input Clock as the Reference
When an input clock is used as the reference, connect
the input clock to X1, leave X2 unconnected, and connect
TUNE to V
DD
.
Crystal Selection
When using a crystal with the MAX9491’s internal oscil-
lator, connect the crystal to X1 and X2. Choose an AT-
cut crystal that oscillates on its fundamental mode with
±30ppm and loading capacitance less than 14pF. To
achieve a wide VCXO tuning range, select a crystal
with motional capacitance greater than 7fF and con-
nect 6pF or less shunt capacitors at both X1 and X2 to
ground. When the VCXO is used as an oscillator, select
both shunt capacitors to approximately 13pF. The opti-
mal shunt capacitors for achieving minimum frequency
offset can be determined experimentally.
