PI90LV018AWE

4
PS8423D 11/11/08
PI90LV032A/PI90LV028A/PI90LV018A
3V LVDS High-Speed Differential Line Receivers
Switching Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 3,4,7,8)
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ZHP
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Notes:
1. “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
2. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless
otherwise specified.
3. All typicals are given for: V
CC
= +3.3V, T
A
= +25°C.
4. Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z
O
= 50Ω, t
R
and t
F
(0% to 100%) ≤ 3ns for R
IN
.
5. The VCMR range is reduced for larger VID. Example : if VID = 400mV, the VCMR is 0.2V to 2.2V. The fail-safe condition with inputs
shorted is valid over a common-mode range of 0V to 2.3V. A VID up tp V
CC
- 0V may be applied to the R
IN+
/ R
IN-
inputs with the
Common-Mode voltage set to V
CC
/2. Propagation delay and Differential Pulse skew decrease when VID is increased from 200mV to
400mV. Skew specifications apply for 200mVVID 800mV over the common mode range.
6. tskd1 is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the
same channel.
7. t
SKD2
, Channel-to-Channel Skew, is defined as the difference between the propagation delay of one channel and that of the others on the
same chip with any event on the inputs.
8. t
SKD3
, Part-to-Part Skew, is the differential Channel-to-Channel skew of any event between devices. This specification applies to devices
at the same V
CC
,and within 5ºC of each other within the operating temperature range.
9. t
SKD4
, Part-to-Part Skew, is the differential Channel-to-Channel skew of any event between devices. This specification applies
to devices over recommended operating temperature and voltage ranges, and across process distribution. tskd4 is defined as IMax - Mini
differential propagation delay.
10. Output short circuit current (I
OS
) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at
a time, do not exceed maximum junction temperature specification.
11. C
L
includes probe and jig capacitance.
12. V
CC
is always higher than R
IN+
and R
IN-
voltage. R
IN-
and R
IN+
are allowed to have a voltage range -0.2V to V
CC
- VID/2.
However, to be compliant with AC specifications, the common voltage range 0.1V to 2.3V.
13. fmax generator input conditions: t
R
= t
F
< 1ns, (0% to 100%), 50% duty cycle, differential (1.05V to1.35V peak to peak).
Output Criteria: duty cycle = 60%/40%, V
OL
(max 0.4V), V
OH
(min 2.7V), Load = 10pF (stray plus probes).
08-0295
5
PS8423D 11/11/08
PI90LV032A/PI90LV028A/PI90LV018A
3V LVDS High-Speed Differential Line Receivers
Parameter Measurement Information
Figure 1. Receiver Propagation Delay and Transition Time Test Circuit
Figure 2. Receiver Propagation Delay and Transition Time Waveforms
t
TLH
20%
R
OUT
V
ID
=
200mV
R
IN-
R
IN+
V
OL
t
PHLD
t
PLHD
+1.3V
+1.1V
1.5V
0V (Differential) +1.2V
1.5V
80% 80%
20%
t
THL
Figure 3. Receiver Three-STATE Delay Test Circuit
EN*
EN
1/4 PI90LV032
Generator
R
OUT
R
L
R
IN+
R
IN-
50:
C
L
S
1
V
CC
DEVICE
UNDER
TEST
C
L
includes load and test jig capacitance.
S
1
= VCC for T
PZL
, and T
PLZ
measurements
S
1
= GND for t
PZH
and t
PHZ
measurements
Generator
Receiver ENABLED
R
IN+
R
OUT
R
R
IN-
C
L
507
507
08-0295
6
PS8423D 11/11/08
PI90LV032A/PI90LV028A/PI90LV018A
3V LVDS High-Speed Differential Line Receivers
Figure 4. Receiver Three-STATE Delay Waveforms
Figure 5. Point-to-Point Application
ANY LVDS DRIVER
Enable
Data
Input
1/4PI90LV032A
Data
Output
RT
+
-
100:
Balanced System
08-0295

PI90LV018AWE

Mfr. #:
Manufacturer:
Description:
IC LVDS DIFF LINE RCVR HS 8-SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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