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NCP5422ADR2G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
NCP5422A
http://onsemi.com
4
ELECTRICAL CHARACTERISTICS (0°C < T
A
< 70°C; 0°C < T
J
< 125°C; R
OSC
= 30.9 k, C
COMP1,2
= 0.1 mF,
10.8
V < V
CC
< 13.2 V; 10.8 V < BST < 20 V, C
GATE(H)1,2
= C
GATE(L)1,2
= 1.0 nF, unless otherwise specified.)
Characteristic
Test Conditions Min Typ Max Unit
Error Amplifier
V
FB1(2)
Bias Current V
FB1(2)
= 0 V - 0.5 1.6
mA
V
FB1(2)
Input Range - 0 - 1.1 V
COMP1,2 Source Current COMP1,2 = 1.2 V to 2.5 V; V
FB1(2)
= 0.8 V 15 30 60
mA
COMP1,2 Sink Current COMP1,2 = 1.2 V; V
FB1(2)
= 1.2 V 15 30 60
mA
Reference Voltage 1(2) COMP1 = V
FB1
; COMP2 = V
FB2
0.980 1.000 1.020 V
COMP1,2 Max Voltage V
FB1(2)
= 0.8 V 3.0 3.3 - V
COMP1,2 Min Voltage V
FB1(2)
= 1.2 V - 0.25 0.35 V
Open Loop Gain - - 95 - dB
Unity Gain Band Width - - 40 - kHz
PSRR @ 1.0 kHz - - 70 - dB
Transconductance - - 32 - mmho
Output Impedance - - 2.5 -
MW
GATE(H) and GATE(L)
High Voltage (AC)
Measure: V
CC
- GATE(L)1, 2;
BST - GATE(H)1,2; Note 2
- 0 0.5 V
Low Voltage (AC) Measure:GATE(L)1,2 or GATE(H)1, 2; Note 2 - 0 0.5 V
Rise Time 1.0 V < GATE(L)1,2 < V
CC
- 1.0 V
1.0 V < GATE(H)1,2 < BST - 1.0 V,
BST ≤ 14 V
- 20 50 ns
Fall Time V
CC
- 1.0 > GATE(L)1,2 > 1.0 V
BST - 1.0 > GATE(H)1,2 > 1.0 V,
BST ≤ 14 V
- 15 50 ns
GATE(H) to GATE(L) Delay GATE(H)1,2 < 2.0 V, GATE(L)1,2 > 2.0 V
BST ≤ 14 V
20 40 70 ns
GATE(L) to GATE(H) Delay GATE(L)1,2 < 2.0 V, GATE(H)1,2 > 2.0 V;
BST ≤ 14 V
20 40 70 ns
GATE(H)1(2) and GATE(L)1(2) pulldown Resistance to GND
Note 2
50 125 280
kW
PWM Comparator
PWM Comparator Offset
V
FFB1(2)
= 0 V; Increase COMP1,2 until
GATE(H)1,2 starts switching
0.30 0.425 0.55 V
Artificial Ramp Duty cycle = 50%, Note 2 40 70 100 mV
Minimum Pulse Width Note 2 - - 300 ns
Oscillator
Switching Frequency R
OSC
= 61.9 k; Measure GATE(H)1; Note 2 112 150 188 kHz
Switching Frequency R
OSC
= 30.9 k; Measure GATE(H)1 250 300 350 kHz
Switching Frequency R
OSC
= 15.1 k; Measure GATE(H)1; Note 2 450 600 750 kHz
R
OSC
Voltage R
OSC
= 30.9 k, Note 2 0.970 1.000 1.030 V
Phase Difference - - 180 - °
2. Guaranteed by design, not 100% tested in production.
NCP5422A
http://onsemi.com
5
ELECTRICAL CHARACTERISTICS (0°C < T
A
< 70°C; 0°C < T
J
< 125°C; R
OSC
= 30.9 k, C
COMP1,2
= 0.1 mF,
10.8
V < V
CC
< 13.2 V; 10.8 V < BST < 20 V, C
GATE(H)1,2
= C
GATE(L)1,2
= 1.0 nF, unless otherwise specified.)
Characteristic UnitMaxTypMinTest Conditions
Supply Currents
V
CC
Current COMP1,2 = 0 V (No Switching) - 13 17 mA
BST Current COMP1,2 = 0 V (No Switching) - 3.5 6.0 mA
Undervoltage Lockout
Start Threshold
GATE(H) Switching; COMP1,2 charging 7.8 8.6 9.4 V
Stop Threshold GATE(H) not switching; COMP1,2 discharging 7.0 7.8 8.6 V
Hysteresis Start-Stop 0.5 0.8 1.5 V
Hiccup Mode Overcurrent Protection
OVC Comparator Offset Voltage
0 V < IS+ 1(2) < 5.5 V, 0 V < IS- 1(2) < 5.5 V 55 70 85 mV
Discharge Threshold - 0.20 0.25 0.30 V
IS+ 1(2) Bias Current 0 V < IS+ 1(2) < 5.5 V -1.0 0.1 1.0
mA
IS- 1(2) Bias Current 0 V < IS- 1(2) < 5.5 V -1.0 0.1 1.0
mA
OVC Common Mode Range Note 3 0 - 5.5 V
OVC Latch COMP1 Discharge Current COMP1 = 1.0 V 2.0 5.0 8.0
mA
OVC Latch COMP2 Discharge Current COMP2 = 1.0 V 0.3 1.2 3.5 mA
COMP1 Charge/Discharge Ratio in OVC - 5.0 6.0 7.0 -
3. Guaranteed by design, not 100% tested in production.
PACKAGE PIN DESCRIPTION
PIN NO. PIN SYMBOL FUNCTION
1 GATE(H)1 High Side Switch FET driver pin for channel 1.
2 GATE(L)1 Low Side Synchronous FET driver pin for channel 1.
3 GND Ground pin for all circuitry contained in the IC. This pin is internally bonded to the substrate of the IC.
4 BST Power input for GATE(H)1 and GATE(H)2 pins.
5 IS+1 Positive input for channel 1 overcurrent comparator.
6 IS-1 Negative input for channel 1 overcurrent comparator.
7 V
FB1
Error amplifier inverting input for channel 1.
8 COMP1 Channel 1 Error Amp output. PWM Comparator reference input. A capacitor to LGND provides Error
Amp compensation. The same capacitor provides Soft-Start timing for channel 1. This pin also
disables the channel 1 output when pulled below 0.3 V.
9 COMP2 Channel 2 Error Amp output. PWM Comparator reference input. A capacitor to LGND provides Error
Amp compensation and Soft-Start timing for channel 2. Channel 2 output is disabled when this pin is
pulled below 0.3 V.
10 V
FB2
Error amplifier inverting input for channel 2.
11 IS-2 Negative input for channel 2 overcurrent comparator.
12 IS+2 Positive input for channel 2 overcurrent comparator.
13 R
OSC
Oscillator frequency pin. A resistor from this pin to ground sets the oscillator frequency.
14 V
CC
Input Power supply pin.
15 GATE(L)2 Low Side Synchronous FET driver pin for channel 2.
16 GATE(H)2 High Side Switch FET driver pin for channel 2.
NCP5422A
http://onsemi.com
6
V
CC
Set
Dominant
IS+1
PWM Com‐
parator 1
PWM Com‐
parator 2
Reset
Dominant
CURRENT
SOURCE
GEN
BST
FAULT
BIAS
FAULT
R
S
R
S
R
S
RAMP1
GATE(H)1
5.0 mA
0.425 V
0.25 V
COMP1
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
COMP2
V
FB1
RAMP2
FAULT
FAULT
Reset
Dominant
GATE(L)1
GATE(H)
2
GATE(L)2
GND
V
CC
BST
V
CC
RAMP1
RAMP2
CLK1
CLK2
OSC
0.425 V
1.0 V
E/A2
E/A OFF
E/A1
E/A OFF
R
OSC
Q
1.2 mA
V
FB2
1.0 V
V
CC
-
+
-
+
IS-1
IS+2
IS-2
-
+
-
+
8.6 V
70 mV
70 mV
BST
Figure 2. Block Diagram
7.8 V
FAULT
FAULT
non-overlap
non-overlap
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

NCP5422ADR2G

Mfr. #:
Buy NCP5422ADR2G
Manufacturer:
ON Semiconductor
Description:
Switching Controllers Dual Out-Of-Phase Synchronous Buck
Lifecycle:
New from this manufacturer.
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