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Selecting the Switching Frequency
Selecting the switching frequency is a trade-off between
component size and power losses. Operation at higher
switching frequencies allows the use of smaller inductor and
capacitor values. Nevertheless, it is common to select lower
frequency operation because a higher frequency results in
lower efficiency due to MOSFET gate charge losses.
Additionally, the use of smaller inductors at higher
frequencies results in higher ripple current, higher output
voltage ripple, and lower efficiency at light load currents.
The value of the oscillator resistor is designed to be
linearly related to the switching period. If the designer
prefers not to use Figure 8 to select the necessary resistor, the
following equation quite accurately predicts the proper
resistance for room temperature conditions.
R
OSC
+
21700 * f
SW
2.31 f
SW
where:
R
OSC
= oscillator resistor in kW;
f
SW
= switching frequency in kHz.
Figure 8. Switching Frequency
10 20 30 40 50 60
100
200
300
400
500
600
700
800
R
OSC
(k
W
)
Frequency (kHz)
Selection of the Output Inductor
The inductor should be selected based on its inductance,
current capability, and DC resistance. Increasing the
inductor value will decrease output voltage ripple, but
degrade transient response. There are many factors to
consider in selecting the inductor including cost, efficiency,
EMI and ease of manufacture. The inductor must be able to
handle the peak current at the switching frequency without
saturating, and the copper resistance in the winding should
be kept as low as possible to minimize resistive power loss.
There are a variety of materials and types of magnetic
cores that could be used for this application. Among them
are ferrites, molypermalloy cores (MPP), amorphous and
powdered iron cores. Powdered iron cores are very
commonly used. Powdered iron cores are very suitable due
to its high saturation flux density and have low loss at high
frequencies, a distributed gap and exhibit very low EMI.
The minimum value of inductance which prevents
inductor saturation or exceeding the rated FET current can
be calculated as follows:
L
MIN
+
(V
IN(MIN)
* V
OUT
) V
OUT
f
SW
V
IN(MIN)
I
SW(MAX)
where:
L
MIN
= minimum inductance value;
V
IN(MIN)
= minimum design input voltage;
V
OUT
= output voltage;
f
SW
= switching frequency;
I
SW(MAX)
- maximum design switch current.
The inductor ripple current can then be determined:
DI
L
+
V
OUT
(1 * D)
L f
SW
where:
DI
L
= inductor ripple current;
V
OUT
= output voltage;
L = inductor value;
D = duty cycle.
f
SW
= switching frequency
The designer can now verify if the number of output
capacitors will provide an acceptable output voltage ripple
(1.0% of output voltage is common). The formula below is
used:
DI
L
+
DV
OUT
ESR
MAX
Rearranging we have:
ESR
MAX
+
DV
OUT
DI
L
where:
ESR
MAX
= maximum allowable ESR;
DV
OUT
= 1.0% × V
OUT
= maximum allowable output
voltage ripple ( budgeted by the designer );
DI
L
= inductor ripple current;
V
OUT
= output voltage.
The number of output capacitors is determined by:
Numberofcapacitors +
ESR
CAP
ESR
MAX
where:
ESR
CAP
= maximum ESR per capacitor (specified in
manufacturer's data sheet).
The designer must also verify that the inductor value
yields reasonable inductor peak and valley currents (the
inductor current is a triangular waveform):
I
L(PEAK)
+ I
OUT
)
DI
L
2
where:
I
L(PEAK)
= inductor peak current;
I
OUT
= load current;
DI
L
= inductor ripple current.
I
L(VALLEY)
+ I
OUT
*
DI
L
2
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where:
I
L(VALLEY)
= inductor valley current.
Input Capacitor Selection
The choice and number of input capacitors is determined
by their voltage and ripple current ratings. The designer
must choose capacitors that will support the worst case input
voltage with an adequate margin. To calculate the number of
input capacitors one must first determine the RMS ripple
current through the capacitors. To this end, first calculate the
average input current to the converter:
I
in(Avg)
+
V
1
·I
1
) V
2
·I
2
h·V
in
wherehistheexpected
efficiency(typical X 85%)
With the average input current determined, the RMS
ripple current through the input capacitor will be:
I
rms
+
ǒ
I
o1
2
)
I
p1
2
3
Ǔ
·D
1
)
ǒ
I
o2
2
)
I
p2
2
3
Ǔ
·D
2
-I
in
2
Ǹ
where:
I
o1,2
is the maximum DC output current for channel 1 and
2 respectively.
I
p1,2
is the peak inductor current (1/2 DI
L
) for channel's
1 and 2 respectively. If the channel peak inductor current
is less than 50% of the channel output current it may be
neglected.
D
1,2
is the channel duty cycle. Here it is assumed that each
channel's duty cycle is less than 50% so that each phase
does not overlap.
Once the RMS ripple current has been determined, the
required number of input capacitor's needed is based on the
rated RMS ripple current rating of the chosen capacitor.
Selection of the Output Capacitors
These components must be selected and placed carefully
to yield optimal results. Capacitors should be chosen to
provide acceptable ripple on the regulator output voltage.
Key specifications for output capacitors are their ESR
(Equivalent Series Resistance), and ESL (Equivalent Series
Inductance). For best transient response, a combination of
low value/high frequency and bulk capacitors placed close
to the load will be required.
In order to determine the number of output capacitors the
maximum voltage transient allowed during load transitions
has to be specified. The output capacitors must hold the
output voltage within these limits since the inductor current
can not change with the required slew rate. The output
capacitors must therefore have a very low ESL and ESR.
The voltage change during the load current transient is:
DV
OUT
+ DI
OUT
ǒ
ESL
Dt
) ESR )
t
TR
C
OUT
Ǔ
where:
DI
OUT
/ Dt = load current slew rate;
DI
OUT
= load transient;
Dt = load transient duration time;
ESL = Maximum allowable ESL including capacitors,
circuit traces, and vias;
ESR = Maximum allowable ESR including capacitors
and circuit traces;
t
TR
= output voltage transient response time.
The designer has to independently assign values for the
change in output voltage due to ESR, ESL, and output
capacitor discharging or charging. Empirical data indicates
that most of the output voltage change (droop or spike
depending on the load current transition) results from the
total output capacitor ESR.
The maximum allowable ESR can then be determined
according to the formula:
ESR
MAX
+
DV
ESR
DI
OUT
where:
DV
ESR
= change in output voltage due to ESR (assigned
by the designer)
Once the maximum allowable ESR is determined, the
number of output capacitors can be found by using the
formula:
Numberofcapacitors +
ESR
CAP
ESR
MAX
where:
ESR
CAP
= maximum ESR per capacitor (specified in
manufacturer's data sheet).
ESR
MAX
= maximum allowable ESR.
The actual output voltage deviation due to ESR can then
be verified and compared to the value assigned by the
designer:
DV
ESR
+ DI
OUT
ESR
MAX
Similarly, the maximum allowable ESL is calculated from
the following formula:
ESL
MAX
+
DV
ESL
Dt
DI
Selection of the Input Inductor
A common requirement is that the buck controller must
not disturb the input voltage. One method of achieving this
is by using an input inductor and a bypass capacitor. The
input inductor isolates the supply from the noise generated
in the switching portion of the buck regulator and also limits
the inrush current into the input capacitors upon power up.
The inductor's limiting effect on the input current slew rate
becomes increasingly beneficial during load transients. The
worst case is when the load changes from no load to full load
(load step), a condition under which the highest voltage
change across the input capacitors is also seen by the input
inductor. The inductor successfully blocks the ripple current
while placing the transient current requirements on the input
bypass capacitor bank, which has to initially support the
sudden load change.
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The minimum inductance value for the input inductor is
therefore:
L
IN
+
DV
(dIńdt)
MAX
where:
L
IN
= input inductor value;
DV = voltage seen by the input inductor during a full load
swing;
(dI/dt)
MAX
= maximum allowable input current slew rate.
The designer must select the LC filter pole frequency so
that at least 40 dB attenuation is obtained at the regulator
switching frequency. The LC filter is a double-pole network
with a slope of -2.0, a roll-off rate of -40 dB/dec, and a
corner frequency:
f
C
+
1
2p LC
Ǹ
where:
L = input inductor;
C = input capacitor(s).
SELECTION OF THE POWER FETS
FET Basics
The use of the MOSFET as a power switch is propelled by
two reasons: 1) Its very high input impedance; and 2) Its very
fast switching times. The electrical characteristics of a
MOSFET are considered to be those of a perfect switch.
Control and drive circuitry power is therefore reduced.
Because the input impedance is so high, it is voltage driven.
The input of the MOSFET acts as if it were a small capacitor,
which the driving circuit must charge at turn on. The lower
the drive impedance, the higher the rate of rise of V
GS
, and
the faster the turn-on time. Power dissipation in the
switching MOSFET consists of 1) conduction losses, 2)
leakage losses, 3) turn-on switching losses, 4) turn-off
switching losses, and 5) gate-transitions losses. The latter
three losses are proportional to frequency.
The most important aspect of FET performance is the
Static Drain-To-Source On-Resistance (R
DS(ON)
), which
affects regulator efficiency and FET thermal management
requirements. The On-Resistance determines the amount of
current a FET can handle without excessive power
dissipation that may cause overheating and potentially
catastrophic failure. As the drain current rises, especially
above the continuous rating, the On-Resistance also
increases. Its positive temperature coefficient is between
+0.6%/°C and +0.85%/°C. The higher the On-Resistance
the larger the conduction loss is. Additionally, the FET gate
charge should be low in order to minimize switching losses
and reduce power dissipation.
Both logic level and standard FETs can be used.
Voltage applied to the FET gates depends on the
application circuit used. Both upper and lower gate driver
outputs are specified to drive to within 1.5 V of ground when
in the low state and to within 2.0 V of their respective bias
supplies when in the high state. In practice, the FET gates
will be driven rail-to-rail due to overshoot caused by the
capacitive load they present to the controller IC.
Selection of the Switching (Upper) FET
The designer must ensure that the total power dissipation
in the FET switch does not cause the power component to
exceed it's maximum rating.
The maximum RMS current through the switch can be
determined by the following formula:
I
RMS(H) +
ƪ
I
L(PEAK)
2
) (I
L(PEAK)
I
L(VALLEY)
)
) I
L(VALLEY)
2
D
ƫ
3
Ǹ
where:
I
RMS(H)
= maximum switching MOSFET RMS current;
I
L(PEAK)
= inductor peak current;
I
L(VALLEY)
= inductor valley current;
D = duty cycle.
Once the RMS current through the switch is known, the
switching MOSFET conduction losses can be calculated:
P
RMS(H)
+ I
RMS(H)
2
R
DS(ON)
where:
P
RMS(H)
= switching MOSFET conduction losses;
I
RMS(H)
= maximum switching MOSFET RMS current;
R
DS(ON)
= FET drain-to-source on-resistance
The upper MOSFET switching losses are caused during
MOSFET switch-on and switch-off and can be determined
by using the following formula:
P
SWH
+ P
SWH(ON)
) P
SWH(OFF)
+
V
IN
I
OUT
(t
RISE
) t
FALL
)
6T
where:
P
SWH(ON)
= upper MOSFET switch-on losses;
P
SWH(OFF)
= upper MOSFET switch-off losses;
V
IN
= input voltage;
I
OUT
= load current;
t
RISE
= MOSFET rise time (from FET manufacturer's
switching characteristics performance curve);
t
FALL
= MOSFET fall time (from FET manufacturer's
switching characteristics performance curve);
T = 1/f
SW
= period.
The total power dissipation in the switching MOSFET can
then be calculated as:
P
HFET(TOTAL)
+ P
RMS(H)
) P
SWH(ON)
) P
SWH(OFF)
where:
P
HFET(TOTAL)
= total switching (upper) MOSFET losses;
P
RMS(H)
= upper MOSFET switch conduction Losses;
P
SWH(ON)
= upper MOSFET switch-on losses;
P
SWH(OFF)
= upper MOSFET switch-off losses;
Once the total power dissipation in the switching FET is
known, the maximum FET switch junction temperature can
be calculated:
T
J
+ T
A
) [P
HFET(TOTAL)
R
qJA
]

NCP5422ADR2

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ON Semiconductor
Description:
IC REG CTRLR BUCK 16SOIC
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