LTM4603HV
7
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pin FuncTions
V
IN
(Bank 1): Power Input Pins. Apply input voltage be-
tween these pins and PGND pins. Recommend placing
input
decoupling capacitance directly between V
IN
pins
and PGND pins.
V
OUT
(Bank 3): Power Output Pins. Apply output load
between these pins and PGND pins. Recommend placing
output decoupling capacitance directly between these pins
and PGND pins. See Figure 17.
PGND (Bank 2): Power ground pins for both input and
output returns.
V
OSNS
(Pin M12): (–) Input to the Remote Sense Ampli-
fier. This pin connects to the ground remote sense point.
The
remote sense amplifier is used for V
OUT
≤3.3V. Tie
to INTV
CC
if not used.
V
OSNS
+
(Pin J12): (+) Input to the Remote Sense Ampli-
fier. This pin connects to the output remote sense point.
The
remote sense amplifier is used for V
OUT
≤3.3V. Tie
to ground if not used.
DIFFV
OUT
(Pin K12): Output of the Remote Sense Amplifier.
This pin connects to the V
OUT_LCL
pin. Leave floating if
remote sense amplifier is not used.
DRV
CC
(Pin E12): This pin normally connects to INTV
CC
for powering the internal MOSFET drivers. This pin can
be biased up to 6V from an external supply with
about
50mA
capability, or an external circuit shown in Figure
18. This improves efficiency at the higher input voltages
by reducing power dissipation in the module.
(See Package Description for Pin Assignment)
INTV
CC
(Pin A7): This pin is for additional decoupling of
the 5V internal regulator.
PLLIN (Pin A8): External Clock Synchronization Input
to the Phase Detector. This pin is internally terminated
to SGND with a 50k resistor. Apply a clock with a high
level above 2V and below INTV
CC
. See the Applications
Information section.
TRACK/SS (Pin A9): Output Voltage Tracking and Soft-
Start Pin. When the module is configured as a master
output, then a soft-start capacitor is placed on this pin
to ground to control the master ramp rate. A soft-start
capacitor can be used for soft-start turn on as a stand
alone regulator. Slave operation is performed by putting
a resistor divider from the master output to ground, and
connecting the center point of the divider to this pin. See
the Applications Information section.
MPGM (Pin A12): Programmable Margining Input. A re
-
sistor from this pin to ground sets a current that is equal
to
1.18V/R. This current multiplied by 10
kΩ will equal a
value in millivolts that is a percentage of the 0.6V refer-
ence voltage
. See the Applications Information section. To
parallel
LTM4603HVs, each requires an individual MPGM
resistor. Do not tie MPGM pins together.
f
SET
(Pin B12): Frequency Set Internally to 1MHz. An
external resistor can be placed from this pin to ground
to increase frequency. See the Applications Information
section for frequency adjustment.
MARG1
DRV
CC
V
FB
PGOOD
SGND
V
OSNS
+
DIFFV
OUT
V
OUT_LCL
V
OSNS
V
IN
PGND
V
OUT
f
SET
MARG0
RUN
COMP
MPGM
PLLIN
INTV
CC
TRACK/SS
LGA PACKAGE
118-LEAD (15mm × 15mm × 2.82mm)
TOP VIEW
LTM4603HV
8
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For more information www.linear.com/LTM4603HV
pin FuncTions
(See Package Description for Pin Assignment)
V
FB
(Pin F12): The Negative Input of the Error Amplifier.
Internally, this pin is connected to V
OUT_LCL
with a 60.4k
precision resistor. Different output voltages can be pro-
grammed with
an additional resistor between V
FB
and
SGND pins. See the Applications Information section.
MARG0 (Pin C12): This pin is the LSB logic input for the
margining function. Together with the MARG1 pin will
determine if margin high, margin low or no margin state
is applied. The pin has an internal pull-down resistor of
50k. See the Applications Information section.
MARG1 (Pin D12): This pin is the MSB logic input for the
margining function. Together with the MARG0 pin will
determine if margin high, margin low or no margin state
is applied. The pin has an internal pull-down resistor of
50k. See the Applications Information section.
SGND (Pin H12): Signal Ground. This pin connects to
PGND at output capacitor point.
COMP (Pin A11): Current Control Threshold and Error
Amplifier Compensation Point. The current comparator
threshold increases with this control voltage. The voltage
ranges from 0V to 2.4V with 0.7V corresponding to zero
sense voltage (zero
current).
PGOOD
(Pin G12): Output Voltage Power Good Indicator.
Open-drain logic output that is pulled to ground when the
output voltage is not within ±10% of the regulation point,
after a 25µs power bad mask timer expires.
RUN (Pin A10): Run Control Pin. A voltage above 1.9V
will turn on the module, and when below 1V, will turn
off the module. A programmable UVLO function can be
accomplished by connecting to a resistor divider from
V
IN
to ground. See Figure 1. This pin has a 5.1V Zener to
ground. Maximum pin voltage is 5V. Limit current into
the RUN pin to less than 1mA.
V
OUT_LCL
(Pin L12): V
OUT
connects directly to this pin to
bypass the remote sense amplifier, or DIFFV
OUT
connects
to this pin when remote sense amplifier is used.
LTM4603HV
9
4603hvfa
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block DiagraM
+
INTERNAL
COMP
SGND
COMP
PGOOD
UVLO
FUNCTION
RUN
R1
V
OUT_LCL
V
IN
>1.9V = ON
<1V = OFF
MAX = 5V
MARG1
MARG0
MPGM
PLLIN
C
SS
INTV
CC
DRV
CC
TRACK/SS
V
FB
f
SET
50k
33.2k
R
SET
19.1k
50k
60.4k
V
OUT
1M
5.1V
ZENER
POWER CONTROL
Q1
V
IN
4.5V TO 28V
V
OUT
2.5V
6A
Q2
10k
10k
10k
50k
10k
2.2Ω
INTV
CC
+
22µF
1.5µF
C
IN
+
C
OUT
PGND
V
OSNS
V
OSNS
+
DIFFV
OUT
4603HV F01
4.7µF
R2
Figure 1. Simplified LTM4603HV Block Diagram
Decoupling requireMenTs
T
A
= 25°C. Use Figure 1 configuration.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
C
IN
External Input Capacitor Requirement
(V
IN
= 4.5V to 28V, V
OUT
= 2.5V)
I
OUT
= 6A 20 µF
C
OUT
External Output Capacitor Requirement
(V
IN
= 4.5V to 28V, V
OUT
= 2.5V)
I
OUT
= 6A 100 200 µF

LTM4603HVIV#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 28V, 6A Step-down Module Regulator with PLL input
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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