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74ALVC16373MTDX

P1-P3P4-P6P7-P8
© 2005 Fairchild Semiconductor Corporation DS500687 www.fairchildsemi.com
October 2001
Revised May 2005
74ALVC16373 Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs
74ALVC16373
Low Voltage 16-Bit Transparent Latch
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch
Enable (LE) is HIGH. When LE is LOW, the data that meets
the setup time is latched. Data appears on the bus when
the Output Enable (OE
) is LOW. When OE is HIGH, the
outputs are in a high impedance state.
The 74ALVC16373 is designed for low voltage (1.1V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74ALVC16373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
■ 1.1V to 3.6V V
CC
supply operation
■ 3.6V tolerant inputs and outputs
■ t
PD
(I
n
to O
n
)
3.5 ns max for 3.0V to 3.6V V
CC
3.9 ns max for 2.3V to 2.7V V
CC
6.8 ns max for 1.65V to 1.95V V
CC
■ Power-off high impedance inputs and outputs
■ Support live insertion and withdrawal (Note 1)
■ Uses patented noise/EMI reduction circuitry
■ Latchup conforms to JEDEC JED78
■ ESD performance:
Human body model
2000V
Machine model 200V
■ Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Note 1: To ensure the high-impedance state during power up or power
down, OE
should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Note 2: BGA package available in Tape and Reel only.
Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Order Number Package Number Package Description
74ALVC16373GX
(Note 2)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
74ALVC16373MTD
(Note 3)
MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
www.fairchildsemi.com 2
74ALVC16373
Connection Diagrams
Pin Assignment for TSSOP
Pin Assignment for FBGA
(Top Thru View)
Pin Descriptions
FBGA Pin Assignments
Truth Tables
H HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial (HIGH or LOW, inputs may not float)
Z
High Impedance
O
0
Previous O
0
before HIGH-to-LOW of Latch Enable
Pin Names Description
OE
n
Output Enable Input (Active LOW)
LE
n
Latch Enable Input
I
0
–I
15
Inputs
O
0
–O
15
Outputs
NC No Connect
123456
A O
0
NC OE
1
LE
1
NC I
0
B O
2
O
1
NC NC I
1
I
2
C O
4
O
3
V
CC
V
CC
I
3
I
4
D O
6
O
5
GND GND I
5
I
6
E O
8
O
7
GND GND I
7
I
8
F O
10
O
9
GND GND I
9
I
10
G O
12
O
11
V
CC
V
CC
I
11
I
12
H O
14
O
13
NC NC I
13
I
14
J O
15
NC OE
2
LE
2
NC I
15
Inputs Outputs
LE
1
OE
1
I
0
–I
7
O
0
–O
7
XHXZ
HLLL
HLHH
LLXO
0
Inputs Outputs
LE
2
OE
2
I
8
–I
15
O
8
–O
15
XHXZ
HLLL
HLHH
LLXO
0
3 www.fairchildsemi.com
74ALVC16373
Functional Description
The 74ALVC16373 contains sixteen edge D-type latches
with 3-STATE outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. Control pins can be shorted together to obtain full
16-bit operation. The following description applies to each
byte. When the Latch Enable (LE
n
) input is HIGH, data on
the I
n
enters the latches. In this condition the latches are
transparent, i.e., a latch output will change state each time
its I input changes. When LE
n
is LOW, the latches store
information that was present on the I inputs a setup time
preceding the HIGH-to-LOW transition on LE
n
. The
3-STATE outputs are controlled by the Output Enable
(OE
n
) input. When OE
n
is LOW the standard outputs are in
the 2-state mode. When OE
n
is HIGH, the standard outputs
are in the high impedance mode but this does not interfere
with entering new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
P1-P3P4-P6P7-P8

74ALVC16373MTDX

Mfr. #:
Buy 74ALVC16373MTDX
Manufacturer:
ON Semiconductor / Fairchild
Description:
Latches Transparent Latch LV 16Bit 3.6V
Lifecycle:
New from this manufacturer.
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