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IRS20954SPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
Not recommended for new designs. IRS20954SPBF
Please use IRS20957SPBF.
www.irf.com 19
IRS20954S
12V
VDD
IN
CSD
VSS
COM
OCSET
LO
VCC
HO
VS
DT
CSH
VB
-B
Vcc
+B
PWM
VREF
NC
NC
10.4V
Rdd
Figure 18: Supplying V
DD
Charging V
BS
Prior to start
The high-side bootstrap power supply can be charged up through a resistor from the positive supply bus to V
B
pin by utilizing an
internal 20.8 V zener diode clamp between V
B
and V
S
. Advantage of this scheme is to eliminate the minimum duration required
for the initial low-side ON.
To determine the requirement for Rcharge, following condition has to be met;
QBSCHARGE
II >
Where I
CHARGE
is a required charging current through Rcharge
I
QBS
is high-side quiescent current
Note that Rcharge can drain floating supply charge during on state of high-side, which limits maximum PWM modulation index
capability of the system. Rcharge should be large enough not to discharge the floating power supply during the high-side ON.
Figure 19: Bootstrap Supply Pre-Charging
Start-up Sequence (UVLO)
The protection control block monitors the status of the power supply of V
DD
and V
CC
whether the voltages are above the Under
Voltage Lockout threshold. The LO and HO of the IRS20954 are disabled by shutdown until the UVLO of V
CC
and V
DD
are
released and CSD timer capacitor Ct is charged up. After the UVLO of V
CC
is released, CSD pin resets power-on timer. At the
Not recommended for new designs. IRS20954SPBF
Please use IRS20957SPBF.
www.irf.com 20
time the voltage at CSD pin reached the release threshold, V
th1
, shutdown logic enables LO and HO. The OC detection blocks
for the low-side and high-side are disabled until UVLO of V
CC
and V
BS
are released.
Power-down Sequence
As soon as V
DD
or V
CC
reaches the UVLO negative going threshold, protection logic makes LO and HO 0 V to turn off the
MOSFET.
Figure 20: IRS20954 Power-Down Timing Chart
Power Supply Decoupling
As the IRS20954 contains analog circuitry, careful attention to the power supply decoupling should be taken to achieve proper
operation. Ceramic capacitors of 0.1 µF or more close to the power supply pins are recommended.
Please also refer to the application note AN-978 for general considerations of high voltage gate driver IC.
V
SS
Negative Bias Clamping
There is a case that V
SS
can go below the COM potential such as a case missing negative supply in dual supply configuration.
This causes excessive negative V
SS
voltage to damage the IRS20954. It is recommended to have a diode to clamp potential
negative bias to V
SS
, if there is a possibility. A standard recovery 1 A diode such as 1N4002 is sufficient in most cases for this
purpose.
Not recommended for new designs. IRS20954SPBF
Please use IRS20957SPBF.
www.irf.com 21
Figure 21: Negative V
SS
Clamping
Junction Temperature Estimation
The power dissipation in the IRS20954 consists of following dominant items;
- P
MID
: dissipation in floating input logic and protection
- P
LOW
: dissipation in low-side
- P
HIGH
: dissipation in high-side
1. P
MID
: Dissipation in Floating Input Section
The dissipation in floating input section is given by;
DD
DD
DDBUS
LDDZDDMID
V
R
VV
PPP
⋅
−
≈
+=
+
Where
P
ZDD
is dissipation from internal zener diode clamping V
DD
voltage.
P
LDD
is dissipation from internal logic circuitry.
V
+BUS
is positive bus voltage feeding V
DD
from.
R
DD
is a resistor feeding V
DD
from V
+BUS
.
For obtaining a value of R
DD
, refer to Supplying V
DD
section above.
2. P
LOW
: Dissipation in Low-side
The dissipation in low-side includes loss from logic circuitry and loss from driving LO, and is given by;
()
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
++
⋅⋅⋅+⋅=
+=
(int)ggO
O
SWgCCQCC
LOLDDLOW
RRR
R
fQVccVI
PPP
Where
P
LDD
is dissipation from internal logic circuitry.
P
LO
is dissipation from gate drive stage to LO.
R
O
is equivalent output impedance of LO, typically 10 Ω for the IRS20954.
R
g(int)
is internal gate resistance of MOSFET.
R
g
is external gate resistance.
Qg is total gate charge of low-side MOSFET.
3. P
HIGH
: Dissipation in High-side
The dissipation in high-side includes loss from logic circuitry and loss from driving LO and is given by;
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

IRS20954SPBF

Mfr. #:
Buy IRS20954SPBF
Manufacturer:
Infineon Technologies
Description:
IC AMP DGTL AUDIO PROT 16-SOIC
Lifecycle:
New from this manufacturer.
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