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AD8306ARZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
REV. A
AD8306
–9–
the intercept to –108 dBV, by raising the RSSI output voltage for
zero input, and to provide temperature compensation, resulting
in a stable intercept. For zero signal conditions, all the detector
output currents are equal. For a finite input, of either polarity,
their difference is converted by the output interface to a single-
sided voltage nominally scaled 20 mV/dB (400 mV per decade), at
the output VLOG (Pin 16). This scaling is controlled by a sepa-
rate feedback stage, having a tightly controlled transcon-
ductance. A small uncertainty in the log slope and intercept
remains (see Specifications); the intercept may be adjusted (see
Applications).
VPS2
FLTR
VLOG
20mV/dB
COMM
I
SOURCE
>50mA
ON DEMAND
C1
3.5pF
CURRENT
MIRROR
I
SINK
FIXED
1mA
3.3kV3.3kV
125mA
1.3kV1.3kV
TRANSCONDUCTANCE
DETERMINES SLOPE
I
T
LGP
LGN
SUMMED
DETECTOR
OUTPUTS
C
F
250ms
VLOG
Figure 23. Simplified RSSI Output Interface
The RSSI output bandwidth, f
LP
, is nominally 3.5 MHz. This is
controlled by the compensation capacitor C1, which may be
increased by adding an external capacitor, C
F
, between FLTR
(Pin 10) and VLOG (Pin 16). An external 33 pF will reduce f
LP
to 350 kHz, while 360 pF will set it to 35 kHz, in each case with
an essentially one-pole response. In general, the relationships
(for f
LP
in MHz) are:
C
f
pF f
CpF
F
LP
LP
F
=
×
=
×
+
−
12 7 10
35
12 7 10
35
10 6
.
–. ;
.
.
–
(1)
Using a load resistance of 50 Ω or greater, and at any tempera-
ture, the peak output voltage may be at least 2.4 V when using a
supply of 4.5 V, and at least 2.1 V for a 3 V supply, which is
consistent with the maximum permissible input levels. The incre-
mental output resistance is approximately 0.3 Ω at low frequen-
cies, rising to 1 Ω at 150 kHz and 18 Ω at very high frequencies.
The output is unconditionally stable with load capacitance, but
it should be noted that while the peak sourcing current is
over 100 mA, and able to rapidly charge even large capacitances,
the internally provided sinking current is only 1 mA. Thus, the
fall time from the 2 V level will be as long as 2 µs for a 1 nF
load. This may be reduced by adding a grounded load resistance.
USING THE AD8306
The AD8306 exhibits very high gain from 1 MHz to over 1 GHz,
at which frequency the gain of the main path is still over 65 dB.
Consequently, it is susceptible to all signals, within this very
broad frequency range, that find their way to the input termi-
nals. It is important to remember that these are quite indistin-
guishable from the “wanted” signal, and will have the effect of
raising the apparent noise floor (that is, lowering the useful
dynamic range). Therefore, while the signal of interest may be
an IF of, say, 200 MHz, any of the following could easily be
larger than this signal at the lower extremities of its dynamic
range: a 60 Hz hum, picked up due to poor grounding tech-
niques; spurious coupling from digital logic on the same PC
board; a strong EMI source; etc.
Very careful shielding is essential to guard against such un-
wanted signals, and also to minimize the likelihood of instability
due to HF feedback from the limiter outputs to the input. With
this in mind, the minimum possible limiter gain should be used.
Where only the logarithmic amplifier (RSSI) function is re-
quired, the limiter should be disabled by omitting R
LIM
and
tying the outputs LMHI and LMLO directly to VPS2. A good
ground plane should be used to provide a low impedance con-
nection to the common pins, for the decoupling capacitor(s)
used at VPS1 and VPS2, and at the output ground. Note that
COM2 is a special ground pin serving just the RSSI output.
The four pins labeled PADL tie down directly to the metallic
lead frame, and are thus connected to the back of the chip. The
process on which the AD8306 is fabricated uses a bonded-wafer
technique to provide a silicon-on-insulator isolation, and there is
no junction or other dc path from the back side to the circuitry
on the surface. These paddle pins must be connected directly to
the ground plane using the shortest possible lead lengths to
minimize inductance.
The voltages at the two supply pins should not be allowed to
differ greatly; up to 500 mV is permissible. It is desirable to
allow VPS1 to be slightly more negative than VPS2. When the
primary supply is greater than 2.7 V, the decoupling resistors R1
and R2 (Figure 24) may be increased to improve the isolation
and lower the dissipation in the IC. However, since VPS2 sup-
ports the RSSI load current, which may be large, the value of
R2 should take this into account.
Basic Connections for Log (RSSI) Output
Figure 24 shows the connections required for most applications.
The AD8306 is enabled by connecting ENBL to VPS1. The
device is put into the sleep mode by grounding this pin. The
inputs are ac-coupled by C1 and C2, which normally should
have the same value (C
C
). The input is, in this case, terminated
with a 52.3 Ω resistor that combines with the AD8306’s input
resistance of 1000 Ω to give a broadband input impedance of
50 Ω. Alternatively an input matching network can be used (see
Input Matching section).
1
2
3
4
5
6
7
8
VLOG
VPS2
PADL
LMHI
LMLO
PADL
FLTR
LMDR
COM2
VPS1
PADL
INHI
INLO
PADL
COM1
ENBL
AD8306
9
10
11
14
15
16
0.1mF
R2
10V
RSSI
0.1mF
R1
10V
ENABLE
R
T
52.3V
C1
0.01mF
SIGNAL
INPUTS
12
13
V
S
(2.7V TO 6.5V)
C2
0.01mF
C
F
(OPTIONAL
SEE TEXT)
Figure 24. Basic Connections for RSSI (Log) Output
The 0.01 µF coupling capacitors and the resulting 50 Ω input
impedance give a high-pass corner frequency of around 600 kHz.
(1/(2 π RC)), where C = (C1)/2. In high frequency applications,
this corner frequency should be placed as high as possible, to
minimize the coupling of unwanted low frequency signals. In
REV. A
AD8306
–10–
low frequency applications, a simple RC network forming a low-
pass filter should be added at the input for the same reason.
If the limiter output is not required, Pin 9 (LMDR) should be
left open and Pins 12 and 13 (LMHI, LMLO) should be tied to
VPS2 as shown in Figure 24.
Figure 25 shows the output versus the input level in dBV, for
sine inputs at 10 MHz, 50 MHz and 100 MHz (add 13 to the
dBV number to get dBm Re 50 Ω. Figure 26 shows the typi-
cal logarithmic linearity (log conformance) under the same
conditions.
INPUT LEVEL – dBV
2.5
–120
RSSI OUTPUT – V
2
1.5
1
0.5
0
–100 –80 –60 –40 –20 0 20
100MHz
50MHz
10MHz
Figure 25. RSSI Output vs. Input Level at T
A
= +25
°
C for
Frequencies of 10 MHz, 50 MHz and 100 MHz
5
–120
ERROR – dB
4
3
2
1
0
–1
–2
–100 –80 –60 –40 –20 20
–3
–4
–5
–100
INPUT LEVEL – dBV
0
DYNAMIC RANGE 61dB 63dB
10MHz 86 93
50MHz 90 97
100MHz 96 100
100MHz
50MHz
10MHz
Figure 26. Log Linearity vs. Input Level at T
A
= +25
°
C, for
Frequencies of 10 MHz, 50 MHz and 100 MHz
Transfer Function in Terms of Slope and Intercept
The transfer function of the AD8306 is characterized in terms
of its Slope and Intercept. The logarithmic slope is defined as
the change in the RSSI output voltage for a 1 dB change at the
input. For the AD8306 the slope is calibrated to be 20 mV/dB.
The intercept is the point at which the extrapolated linear re-
sponse would intersect the horizontal axis. For the AD8306 the
intercept is calibrated to be –108 dBV (–95 dBm). Using the
slope and intercept, the output voltage can be calculated for any
input level within the specified input range using the equation:
V
OUT
= V
SLOPE
× (P
IN
– P
O
) (2)
where V
OUT
is the demodulated and filtered RSSI output,
V
SLOPE
is the logarithmic slope, expressed in V/dB, P
IN
is the
input signal, expressed in decibels relative to some reference
level (either dBm or dBV in this case) and P
O
is the logarithmic
intercept, expressed in decibels relative to the same reference
level.
For example, for an input level of –33 dBV (–20 dBm), the
output voltage will be
V
OUT
= 0.02 V/dB × (–33 dBV – (–108 dBV)) = 1.5 V (3)
The most widely used convention in RF systems is to specify
power in dBm, that is, decibels above 1 mW in 50 Ω. Specifica-
tion of log amp input level in terms of power is strictly a conces-
sion to popular convention; they do not respond to power (tacitly
“power absorbed at the input”), but to the input voltage. The
use of dBV, defined as decibels with respect to a 1 V rms sine wave,
is more precise, although this is still not unambiguous because
waveform is also involved in the response of a log amp, which,
for a complex input (such as a CDMA signal) will not follow the
rms value exactly. Since most users specify RF signals in terms
of power—more specifically, in dBm/50 Ω—we use both dBV
and dBm in specifying the performance of the AD8306, showing
equivalent dBm levels for the special case of a 50 Ω environment.
Values in dBV are converted to dBm re 50 Ω by adding 13.
Output Response Time and C
F
The RSSI output has a low-pass corner frequency of 3.5 MHz,
which results in a 10% to 90% rise time of 73 ns. For low fre-
quency applications, the corner frequency can be reduced by
adding an external capacitor, C
F
, between FLTR (Pin 10) and
VLOG (Pin 16) as shown in Figure 24. For example, an exter-
nal 33 pF will reduce the corner frequency to 350 kHz, while
360 pF will set it to 35 kHz, in each case with an essentially
one-pole response.
Using the Limiter
Figure 27 shows the basic connections for operating the limiter
and the log output concurrently. The limiter output is a pair of
differential currents of magnitude, I
OUT
, from high impedance
(open-collector) sources. These are converted to equal-amplitude
voltages by supply-referenced load resistors, R
LOAD
. The limiter
output current is set by R
LIM
, the resistor connected between
Pin 9 (LMDR) and ground. The limiter output current is set
according the equation:
I
OUT
= –400 mV/R
LIM
(5)
and has an absolute accuracy of ±5%.
The supply referenced voltage on each of the limiter pins will
thus be given by:
V
LIM
= V
S
–400 mV × R
LOAD
/R
LIM
(6)
REV. A
AD8306
–11–
1
2
3
4
5
6
7
8
VLOG
VPS2
PADL
LMHI
LMLO
PADL
FLTR
LMDR
COM2
VPS1
PADL
INHI
INLO
PADL
COM1
ENBL
AD8306
9
10
11
14
15
16
0.1mF
R2
10V
NC
R
LIM
RSSI
0.1mF
R1
10V
ENABLE
R
T
52.3V
C1
0.01mF
SIGNAL
INPUTS
NC = NO CONNECT
12
13
V
S
(2.7V TO 6.5V)
C2
0.01mF
(SEE TEXT)
0.01mF
0.01mF
LIMITER
OUTPUT
R
LOAD
R
L
Figure 27. Basic Connections for Operating the Limiter
Depending on the application, the resulting voltage may be used
in a fully balanced or unbalanced manner. It is good practice to
retain both load resistors, even when only one output pin is
used. These should always be returned to the same well de-
coupled node on the PC board (see layout of evaluation board).
The unbalanced, or single-sided mode, is more inclined to result
in instabilities caused by the very high gain of the signal path.
The limiter current may be set as high as 10 mA (which requires
R
LIM
to be 40 Ω) and can be optionally increased somewhat
beyond this level. It is generally inadvisable, however, to use a
high bias current, since the gain of this wide bandwidth signal
path is proportional to the bias current, and the risk of instabil-
ity is elevated as R
LIM
is reduced (recommended value is 400 Ω).
However, as the size of R
LOAD
is increased, the bandwidth of the
limiter output decreases from 585 MHz for R
LOAD
= R
LIM
=
50 Ω to 50 MHz for R
LOAD
= R
LIM
= 400 Ω (bandwidth =
210 MHz for R
LOAD
= R
LIM
= 100 Ω and 100 MHz for R
LOAD
=
R
LIM
= 200 Ω). As a result, the minimum necessary limiter
output level should be chosen while maintaining the required
limiter bandwidth. For R
LIM
= R
LOAD
= 50 Ω, the limiter output
is specified for input levels between –78 dBV (–65 dBm) and
+9 dBV (+22 dBm). The output of the limiter may be unstable
for levels below –78 dBV (–65 dBm). However, keeping R
LIM
above 100 Ω will make instabilities on the output less likely for
input levels below –78 dBV.
A transformer or a balun (e.g., MACOM part number ETC1-1-13)
can be used to convert the differential limiter output voltages to
a single-ended signal.
Input Matching
Where either a higher sensitivity or a better high frequency
match is required, an input matching network is valuable. Using
a flux-coupled transformer to achieve the impedance transfor-
mation also eliminates the need for coupling capacitors, lowers
any dc offset voltages generated directly at the input, and use-
fully balances the drives to INHI and INLO, permitting full
utilization of the unusually large input voltage capacity of the
AD8306.
The choice of turns ratio will depend somewhat on the fre-
quency. At frequencies below 30 MHz, the reactance of the
input capacitance is much higher than the real part of the input
impedance. In this frequency range, a turns ratio of 2:9 will
lower the effective input impedance to 50 Ω while raising the
input voltage by 13 dB. However, this does not lower the effect
of the short circuit noise voltage by the same factor, since there
will be a contribution from the input noise current. Thus, the
total noise will be reduced by a smaller factor. The intercept at
the primary input will be lowered to –121 dBV (–108 dBm).
Impedance matching and drive balancing using a flux-coupled
transformer is useful whenever broadband coupling is required.
However, this may not always be convenient. At high frequen-
cies, it will often be preferable to use a narrow-band matching
network, as shown in Figure 28, which has several advantages.
First, the same voltage gain can be achieved, providing increased
sensitivity, but now a measure of selectively is simultaneously
introduced. Second, the component count is low: two capacitors
and an inexpensive chip inductor are needed. Third, the net-
work also serves as a balun. Analysis of this network shows that
the amplitude of the voltages at INHI and INLO are quite simi-
lar when the impedance ratio is fairly high (i.e., 50 Ω to 1000 Ω).
1
2
3
4
5
6
7
8
VLOG
VPS2
PADL
LMHI
LMLO
PADL
FLTR
LMDR
COM2
VPS1
PADL
INHI
INLO
PADL
COM1
ENBL
AD8306
9
10
11
14
15
16
0.1mF
10V
NC
R
LIM
RSSI
LIMITER
OUTPUT
0.1mF
10V
C2 = C
M
Z
IN
NC = NO CONNECT
12
13
V
S
C1 = C
M
L
M
Figure 28. High Frequency Input Matching Network
Figure 29 shows the response for a center frequency of 100 MHz.
The response is down by 50 dB at one-tenth the center frequency,
falling by 40 dB per decade below this. The very high frequency
attenuation is relatively small, however, since in the limiting
case it is determined simply by the ratio of the AD8306’s input
capacitance to the coupling capacitors. Table I provides solu-
tions for a variety of center frequencies f
C
and matching from
impedances Z
IN
of nominally 50 Ω and 100 Ω. Exact values are
shown, and some judgment is needed in utilizing the nearest
standard values.
FREQUENCY – MHz
14
60
DECIBELS
13
12
11
10
9
8
7
6
5
70 80 90 100 110 120 130
4
3
2
1
0
–1
140 150
GAIN
INPUT AT
TERMINATION
Figure 29. Response of 100 MHz Matching Network
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AD8306ARZ

Mfr. #:
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Manufacturer:
Analog Devices Inc.
Description:
Logarithmic Amplifiers 100 dB-range 10nA-1mA
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