REV. A
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a
AD8306
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
5 MHz–400 MHz 100 dB High Precision
Limiting-Logarithmic Amplifier
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Complete, Fully Calibrated Log-Limiting IF Amplifier
100 dB Dynamic Range: –91 dBV to +9 dBV
Stable RSSI Scaling Over Temperature and Supplies:
20 mV/dB Slope, –95 dBm Intercept
0.4 dB RSSI Linearity up to 200 MHz
Programmable Limiter Gain and Output Current
Differential Outputs to 10 mA, 2.4 V p-p
Overall Gain 90 dB, Bandwidth 400 MHz
Constant Phase (Typical 56 ps Delay Skew)
Single Supply of +2.7 V to +6.5 V at 16 mA Typical
Fully Differential Inputs, R
IN
= 1 k, C
IN
= 2.5 pF
500 ns Power-Up Time, <1 A Sleep Current
APPLICATIONS
Receivers for Frequency and Phase Modulation
Very Wide Range IF and RF Power Measurement
Receiver Signal Strength Indication (RSSI)
Low Cost Radar and Sonar Signal Processing
Instrumentation: Network and Spectrum Analyzers
PRODUCT DESCRIPTION
The AD8306 is a complete IF limiting amplifier, providing both
an accurate logarithmic (decibel) measure of the input signal
(the RSSI function) over a dynamic range of 100 dB, and a
programmable limiter output, useful from 5 MHz to 400 MHz.
It is easy to use, requiring few external components. A single
supply voltage of +2.7 V to +6.5 V at 16 mA is needed, corre-
sponding to a power consumption of under 50 mW at 3 V, plus
the limiter bias current, determined by the application and typi-
cally 2 mA, providing a limiter gain of 90 dB when using 200
loads. A CMOS-compatible control interface can enable the
AD8306 within about 500 ns and disable it to a standby current
of under 1 µA.
The six cascaded amplifier/limiter cells in the main path have a
small signal gain of 12.04 dB (×4), with a –3 dB bandwidth of
850 MHz, providing a total gain of 72 dB. The programmable
output stage provides a further 18 dB of gain. The input is fully
differential and presents a moderately high impedance (1 k in
parallel with 2.5 pF). The input-referred noise-spectral-density,
when driven from a terminated 50 , source is 1.28 nV/Hz,
equivalent to a noise figure of 3 dB. The sensitivity of the
AD8306 can be raised by using an input matching network.
Each of the main gain cells includes a full-wave detector. An
additional four detectors, driven by a broadband attenuator, are
used to extend the top end of the dynamic range by over 48 dB.
The overall dynamic range for this combination extends from
–91 dBV (–78 dBm at the 50 level) to a maximum permissible
value of +9 dBV, using a balanced drive of antiphase inputs each of
2 V in amplitude, which would correspond to a sine wave power
of +22 dBm if the differential input were terminated in 50 .
Through laser trimming, the slope of the RSSI output is closely
controlled to 20 mV/dB, while the intercept is set to –108 dBV
(–95 dBm re 50 ). These scaling parameters are determined
by a band-gap voltage reference and are substantially indepen-
dent of temperature and supply. The logarithmic law conform-
ance is typically within ±0.4 dB over the central 80 dB of this
range at any frequency between 10 MHz and 200 MHz, and is
degraded only slightly at 400 MHz.
The RSSI response time is nominally 73 ns (10%–90%). The
averaging time may be increased without limit by the addition of
an external capacitor. The full output of 2.34 V at the maximum
input of +9 dBV can drive any resistive load down to 50 and
this interface remains stable with any value of capacitance on
the output.
The AD8306 is fabricated on an advanced complementary
bipolar process using silicon-on-insulator isolation techniques
and is available in the industrial temperature range of –40°C to
+85°C, in a 16-lead narrow body SO package. The AD8306 is
also available for the full military temperature range of –55°C to
+125°C, in a 16-lead side-brazed ceramic DIP.
12dB LIM
DET
12dB
DET DET4 3 DET
LADR ATTEN
INHI
INLO
I–V
BIAS
CTRL
TEN DETECTORS SPACED 12dB
INTERCEPT
TEMP COMP
BAND-GAP
REFERENCE
ENBL
GAIN
BIAS
LMHI
LMLO
LMDR
VLOG
FLTR
SIX STAGES TOTAL GAIN 72dB TYP GAIN 18dB
SLOPE
BIAS
12dB
AD8306* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
EVALUATION KITS
AD8306 Evaluation Board
DOCUMENTATION
Application Notes
AN-1040: RF Power Calibration Improves Performance of
Wireless Transmitters
AN-691: Operation of RF Detector Products at Low
Frequency
Data Sheet
AD8306: 5 MHz-400 MHz 100 dB High Precision Limiting-
Logarithmic Amplifier Data Sheet
AD8306: Military Data Sheet
TOOLS AND SIMULATIONS
ADIsimPLL™
ADIsimRF
REFERENCE MATERIALS
Product Selection Guide
RF Source Booklet
Technical Articles
Design a Logamp RF Pulse Detector
Detecting Fast RF Bursts using Log Amps
Log Amps and Directional Couplers Enable VSWR
Detection
Make Precise Base-Station Power Measurements
Measurement and Control of RF Power, Part I
Measurement and Control of RF Power, Part II
Measurement and Control of RF Power, Part III
Measuring the RF Power in CDMA2000 and W-CDMA High
Power Amplifiers (HPAs)
Measuring VSWR and Gain in Wireless Systems
DESIGN RESOURCES
AD8306 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
View all AD8306 EngineerZone Discussions.
SAMPLE AND BUY
Visit the product page to see pricing options.
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
DOCUMENT FEEDBACK
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REV. A
–2–
AD8306–SPECIFICATIONS
Parameter Conditions Min
1
Typ Max
1
Units
INPUT STAGE (Inputs INHI, INLO)
Maximum Input
2
Differential Drive, p-p ±3.5 ±4V
+9 dBV
Equivalent Power in 50 Terminated in 52.3 R
IN
+22 dBm
Noise Floor Terminated 50 Source 1.28 nV/Hz
Equivalent Power in 50 400 MHz Bandwidth –78 dBm
Input Resistance From INHI to INLO 800 1000 1200
Input Capacitance From INHI to INLO 2.5 pF
DC Bias Voltage Either Input 1.725 V
LIMITING AMPLIFIER (Outputs LMHI, LMLO)
Usable Frequency Range 5 400 MHz
At Limiter Output R
LOAD
= R
LIM
= 50 , to –10 dB Point 585 MHz
Phase Variation at 100 MHz Over Input Range –73 dBV to –3 dBV ±2 Degrees
Limiter Output Current Nominally 400 mV/R
LIM
0110mA
Versus Temperature –40°C T
A
+85°C –0.008 %/°C
Input Range
3
–78 +9 dBV
Maximum Output Voltage At Either LMHI or LMLO, wrt VPS2 1 1.25 V
Rise/Fall Time (10%–90%) R
LOAD
= 50 , 40 R
LIM
400 0.6 ns
LOGARITHMIC AMPLIFIER (Output VLOG)
±3 dB Error Dynamic Range From Noise Floor to Maximum Input 100 dB
Transfer Slope
4
f = 10 MHz 19.5 20 20.5 mV/dB
f = 100 MHz 19.6 mV/dB
Over Temperature –40°C < T
A
< +85°C 19.3 20 20.7 mV/dB
Intercept (Log Offset)
4
f = 10 MHz –109.5 –108 –106.5 dBV
f = 100 MHz –108.4 dBV
Over Temperature –40°C T
A
+85°C –111 –108 –105 dBV
Temperature Sensitivity –0.009 dB/°C
Linearity Error (Ripple) Input from –80 dBV to +0 dBV ±0.4 dB
Output Voltage Input = –91 dBV, V
S
= +5 V, +2.7 V 0.34 V
Input = +9 dBV, V
S
= +5 V 2.34 2.75 V
Input = –3 dBV, V
S
= +3 V 2.10 V
Minimum Load Resistance, R
L
40 50
Maximum Sink Current To Ground 0.75 1.0 1.25 mA
Output Resistance 0.3
Small-Signal Bandwidth 3.5 MHz
Output Settling Time to 2% Large Scale Input, +3 dBV, R
L
␣ 50 , C
L
␣ 100 pF 120 220 ns
Rise/Fall Time (10%–90%) Large Scale Input, +3 dBV, R
L
␣ 50 , C
L
␣ 100 pF 73 100 ns
POWER INTERFACES
Supply Voltage, V
S
2.7 5 6.5 V
Quiescent Current Zero-Signal, LMDR Open 13 16 20 mA
Over Temperature –40°C < T
A
< +85°C 111623mA
Disable Current –40°C < T
A
< +85°C 0.01 4 µA
Additional Bias for Limiter R
LIM
= 400 (See Text) 2.0 2.25 mA
Logic Level to Enable Power HI Condition, –40°C < T
A
< +85°C 2.7 V
S
V
Input Current when HI 3 V at ENBL, –40°C < T
A
< +85°C4060µA
Logic Level to Disable Power LO Condition, –40°C < T
A
< +85°C –0.5 1 V
TRANSISTOR COUNT # of Transistors 207 207
NOTES
1
Minimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values.
2
The input level is specified in “dBV” since logarithmic amplifiers respond strictly to voltage, not power. 0 dBV corresponds to a sinusoidal single-frequency input of
1 V rms. A power level of 0 dBm (1 mW) in a 50 termination corresponds to an input of 0.2236 V rms. Hence, in the special case of 50 termination, dBV values
can be converted into dBm by adding a fixed offset of +13 to the dBV rms value.
3
Due to the extremely high Gain Bandwidth Product of the AD8306, the output of either LMHI or LMLO will be unstable for levels below –78 dBV (–65 dBm, re 50 ).
4
Standard deviation remains essentially constant over frequency. See Figures 13, 14, 16 and 17.
Specifications subject to change without notice.
(V
S
= +5 V, T
A
= +25C, f = 10 MHz, unless otherwise noted)

AD8306AR-REEL7

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Logarithmic Amplifiers 100 dB-range 10nA-1mA
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