PI74LPT16374CAE

PI74LPT16374
3.3V 16-Bit Register (3-State)
4
PS2070F 11/10/08
Power Supply Characteristics
Parameters De scrip tion
Test Conditions
(1)
Min.
Typ
(2)
Max. Units
I
CC
Quiescent Power Supply
Current
V
CC
= Max.
V
IN
= GND or
V
CC
0.1 10
ΜA
ΔI
CC
Quiescent Power Supply
Current TTL Inputs HIGH
V
CC
= Max.
V
IN
= V
CC
– 0.6V
(3)
500
I
CCD
Dynamic Power Supply
(4)
V
CC
= Max.,
Outputs Open
XOE = GND
xLE = V
CC
One Bit Toggling
50% Duty Cycle
V
IN
= V
CC
V
IN
= GND
50 75
μA/
MHz
I
C
Total Power Supply
Current
(6)
V
CC
= Max.,
Outputs Open
fI = 10 MHZ
50% Duty Cycle
XOE = GND
One Bit Toggling
V
IN
= V
CC
– 0.6V
V
IN
= GND
0.6 2.3
mA
V
CC
= Max.,
Outputs Open
fI = 2.5 MHZ
50% Duty Cycle
XOE = GND
16 Bits Toggling
V
IN
= V
CC
– 0.6V
V
IN
= GND
2.1
4.7
(5)
Notes:
1. For Max. or Min. conditions, use appropriate value speci ed under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. I
C =IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ΔICC DHNT + ICCD (fCP/2 + fINI)
I
CC = Quiescent Current (ICCL, ICCH and ICCZ)
ΔI
CC = Power Supply Current for a TTL High Input
D
H = Duty Cycle for TTL Inputs High
N
T = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP = Number of Clock Inputs at fCP
fI = Input Frequency
N
I = Number of Inputs at fI
All currents are in milliamps and all frequencies are in megahertz.
08-0291
PI74LPT16374
3.3V 16-Bit Register (3-State)
5
PS2070F 11/10/08
Switching Characteristics over Operating Range
(1)
Parameters De scrip tion
Test
Conditions
(2)
LPT16374 LPT16374A LPT16374C
UnitsCom. Com. Com.
Min.
(3)
Max. Min.
(3)
Max. Min.
(3)
Max.
t
PLH
t
PHL
Propagation Delay
xCLK to xOx
C
L
= 50pF
RL = 500Ω
2.0 7.0 2.0 6.5 2.0 5.2
ns
t
PZH
t
PZL
Output Enable Time
xOE to xOx
1.5 7.2 1.5 6.5 1.5 5.5
t
PHZ
t
PLZ
Output Disable Time
(4)
xOE to xOx
1.5 7.2 1.5 5.5 1.5 5.0
t
SU
Setup Time HIGH
or LOW, xDx to xCLK
2.0 2.0 2.0
t
H
Hold Time HIGH
or LOW, xDx to xCLK
1.5 1.5 1.5
t
W
xCLK Pulse Width
(4)
HIGH
7.0 5.0 5.0
t
SK(O)
Output Skew
(5)
0.5 0.5 0.5
Notes:
1. Propagation Delays and Enable/Disable times are with Vcc = 3.3V ±0.3V, normal range. For V
CC
= 2.7V, extended range, all Propagation
Delays and Enable/Disable times should be degraded by 20%.
2. For Max. or Min. conditions, use appropriate value speci ed under Electrical Characteristics for the applicable device.
3. Minimum limits are guaranteed but not tested on Propagation Delays.
4. This parameter is guaranteed but not production tested.
5. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guar an teed by design.
08-0291
PI74LPT16374
3.3V 16-Bit Register (3-State)
6
PS2070F 11/10/08
Packaging Mechanical: 48-pin TSSOP (A)
.236
.244
.488
.496
.002
.006
SEATING PLANE
.007
.010
.0197
BSC
.004
.008
.319
1
48
12.4
12.6
6.0
6.2
0.50 0.17
0.27
8.1
0.05
0.15
0.09
0.20
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
.018
.030
0.45
0.75
.047
1.20 Max
BSC
DOCUMENT CONTROL NO.
PD - 1501
REVISION: G
DATE: 03/09/05
Note:
1. Controlling dimensions in millimeters.
2. Ref: JEDEC MO-153F/ED
3. Dimension does not include mold ash, protrusions or gate burrs. Mold ash, protru-
sions and gate burrs shall not exceed 0.15mm per side.
4. Dimension does not include interlead ash or protrusion. Interlead ash or protrusion
shall not exceed 0.25mm per side.
DESCRIPTION: 48-Pin 240-Mil Wide TSSOP
PACKAGE CODE: A
Pericom Semiconductor Corporation
3545 N. 1st Street, San Jose, CA 95134
1-800-435-2335 • www.pericom.com
See Note 3
See Note 4
08-0291

PI74LPT16374CAE

Mfr. #:
Manufacturer:
Description:
Flip Flops 16B Octal Registe
Lifecycle:
New from this manufacturer.
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