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AD7568BP-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15
AD7568
–3–
TIMING SPECIFICATIONS
Limit at Limit at
Parameter T
A
= +258CT
A
= –408C to +858C Units Description
t
1
100 100 ns min CLKIN Cycle Time
t
2
40 40 ns min CLKIN High Time
t
3
40 40 ns min CLKIN Low Time
t
4
30 30 ns min FSIN Setup Time
t
5
30 30 ns min Data Setup Time
t
6
5 5 ns min Data Hold Time
t
7
90 90 ns min FSIN Hold Time
t
8
2
70 70 ns max SDOUT Valid After CLKIN Falling Edge
t
9
40 40 ns min LDAC, CLR Pulse Width
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
t
8
is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
CLKIN (I)
SDIN (I)
SDOUT (O)
DB15 DB0
DB15
DB0
FSIN (I)
LDAC, CLR
t
1
t
4
t
7
t
2
t
3
t
6
t
5
t
8
t
9
NOTES
1. AO IS HARDWIRED HIGH OR LOW.
Figure 1. Timing Diagram
(V
DD
= +5 V 6 5%; I
OUT1
= I
OUT2
= 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted)
1.6mA I
OL
+2.1V
I
OH
200µA
C
L
50pF
TO OUTPUT
PIN
Figure 2. Load Circuit for Digital Output
Timing Specifications
AD7568
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted
Parameter Rating
V
DD
to DGND −0.3 V to +6 V
I
OUT1
to DGND −0.3 V to V
DD
+0.3 V
I
OUT2
to DGND −0.3 V to V
DD
+0.3 V
Digital Input Voltage to DGND −0.3 V to V
DD
+0.3 V
V
RFB
, V
REF
to DGND ±15 V
Input Current to Any Pin Except Supplies
1
±10 mA
Operating Temperature Range
Commercial Plastic (B Versions) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Power Dissipation (Any Package) to 75°C 250 mW
Derates above 75°C by 10 mW/°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
1
Transient currents of up to 100 mA will not cause SCR latch-up.
PIN DESCRIPTION
Mnemonic Description
V
DD
Positive Power Supply. This is 5 V ± 5%.
DGND Digital Ground.
AGND Analog Ground
V
REFA
to V
REFH
DAC Reference Inputs.
R
FBA
to R
FBH
DAC Feedback Resistor Pins.
I
OUTA
to I
OUTH
DAC Current Output Terminals.
AGND This pin connects to the back gates of the current steering switches. It should be connected to the signal ground of the system.
CLKIN
Clock Input. Data is clocked into the input shift register on the falling edges of CLKIN. Add a pull-down resistor on the clock
line to avoid timing issues.
FSIN Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When FSIN goes low, it
enables the input shift register, and data is transferred on the falling edges of CLKIN. If the address bit is valid, the 12-bit DAC
data is transferred to the appropriate input latch on the sixteenth falling edge after FSIN
goes low.
SDIN
Serial Data Input. The device accepts a 16-bit word. The first bit (DB15) is the DAC MSB, with the remaining bits following.
Next comes the device address bit, A0. If this does not correspond to the logic level on Pin A0, the data is ignored. Finally
comes the three DAC select bits. These determine which DAC in the device is selected for loading.
SDOUT This shift register output allows multiple devices to be connected in a daisy-chain configuration.
A0
Device Address Pin. This input gives the device an address. If DB3 of the serial input stream does not correspond to this, the
data that follows is ignored and not loaded to any input latch. However, it will appear at SDOUT irrespective of this.
LDAC Asynchronous LDAC Input. When this input is taken low, all DAC latches are simultaneously updated with the contents of the
input latches.
CLR Asynchronous CLR Input. When this input is taken low, all DAC latch outputs go to zero.
– 4 –
REV. C
AD7568
–5–
TERMINOLOGY
Relative Accuracy
Relative Accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero error and full-scale error and is normally ex-
pressed in Least Significant Bits or as a percentage or full-scale
reading.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
Gain Error
Gain Error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s in
the DAC after offset error has been adjusted out and is
expressed in Least Significant Bits. Gain error is adjustable to
zero with an external potentiometer.
Output Leakage Current
Output leakage current is current which flows in the DAC lad-
der switches when these are turned off. For the I
OUT1
terminal,
it can be measured by loading all 0s to the DAC and measuring
the I
OUT1
current. Minimum current will flow in the I
OUT2
line
when the DAC is loaded with all 1s. This is a combination of
the switch leakage current and the ladder termination resistor
current. The I
OUT2
leakage current is typically equal to that in
I
OUT1
.
Output Capacitance
This is the capacitance from the I
OUT1
pin to AGND.
Output Voltage Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change. For the AD7568, it
is specified with the AD843 as the output op amp.
Digital to Analog Glitch Impulse
This is the amount of charge injected into the analog output
when the inputs change state. It is normally specified as the area
of the glitch in either pA-secs or nV-secs, depending upon
whether the glitch is measured as a current or voltage signal. It
is measured with the reference input connected to AGND and
the digital inputs toggled between all 1s and all 0s.
AC Feedthrough Error
This is the error due to capacitive feedthrough from the DAC
reference input to the DAC I
OUT
terminal, when all 0s are
loaded in the DAC.
Channel-to-Channel Isolation
Channel-to-channel isolation refers to the proportion of input
signal from one DAC’s reference input which appears at the
output of any other DAC in the device and is expressed in dBs.
Digital Crosstalk
The glitch impulse transferred to the output of one converter
due to a change in digital input code to the other converter is
defined as the Digital Crosstalk and is specified in nV-secs.
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device digital inputs is capacitively coupled through the de-
vice to show up as noise on the I
OUT
pin and subsequently on
the op amp output. This noise is digital feedthrough.
Table I. AD7568 Loading Sequence
DB15 DB0
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 A0 DS2 DS1 DS0
Table II. DAC Selection
DS2 DS1 DS0 Function
0 0 0 DAC A Selected
0 0 1 DAC B Selected
0 1 0 DAC C Selected
0 1 1 DAC D Selected
1 0 0 DAC E Sclected
1 0 1 DAC F Selected
1 1 0 DAC G Sclected
1 1 1 DAC H Selected
P1-P3P4-P6P7-P9P10-P12P13-P15

AD7568BP-REEL

Mfr. #:
Buy AD7568BP-REEL
Manufacturer:
Analog Devices Inc.
Description:
IC DAC 12BIT LC2MOS OCTAL 44PLCC
Lifecycle:
New from this manufacturer.
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