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MAX3625CUG+T

P1-P3P4-P6P7-P9P10-P10
MAX3625
Low-Jitter, Precision Clock Generator
with Three Outputs
_______________________________________________________________________________________ 7
Table 2. Output Divider Configuration Chart
INPUT
SELA1/SELB1 SELA0/SELB0
NA/NB DIVIDER
0 0 / 1*
0 1 / 2*
1 0 / 4
1 1 / 5
Table 4. Crystal Selection Parameters
PARAMETER SYMBOL MIN TYP MAX UNITS
Crystal Oscillation
f
OSC
24.8 27 MHz
Shunt Capacitance C
O
2.0 7.0 pF
Load Capacitance C
L
18 pF
Equivalent Series
Resistance (ESR)
R
S
50 Ω
Maximum Crystal
Drive Level
300 µW
Table 1. Output Frequency Determination Chart
*Maximum guaranteed output frequency is 320MHz.
Table 3. PLL Divider Configuration Chart
FB_SEL INPUT M DIVIDER
0 / 25
1 / 24
Figure 2. Crystal Layout
X_IN
X_OUT
27pF
CRYSTAL
(C
L
= 18pF)
33pF
Figure 3. Crystal, Capacitors Connection
CRYSTAL OR
CMOS INPUT
FREQUENCY
(MHz)
FEEDBACK
DIVIDER, M
VCO
FREQUENCY
(MHz)
OUTPUT
DIVIDER,
NA AND NB
OUTPUT
FREQUENCY
(MHz)
APPLICATIONS
2 312.5
4 156.25
25 25 625
5 125
Ethernet
25.78125 25 644.53125 4 161.132812 10Gbps Ethernet
2 312.5
4 156.25
26.04166 24 625
5 125
Ethernet
2 318.75
26.5625 24 637.5
4 159.375
10G Fibre Channel
MAX3625
Low-Jitter, Precision Clock Generator
with Three Outputs
8 _______________________________________________________________________________________
Interfacing with LVPECL Outputs
The equivalent LVPECL output circuit is given in Figure 7.
These outputs are designed to drive a pair of 50Ω trans-
mission lines terminated with 50Ω to V
TT
= V
CC
- 2V. If a
separate termination voltage (V
TT
) is not available, other
terminations methods can be used such as shown in
Figures 4 and 5. Unused outputs should be disabled and
may be left open. For more information on LVPECL termi-
nations and how to interface with other logic families,
refer to Maxim Application Note
HFAN-01.0: Introduction
to LVDS, PECL, and CML
.
Interface Models
Figures 6 and 7 show examples of interface models.
MAX3625
Qx
82Ω
Z
0
= 50Ω
Qx
Z
0
= 50Ω
82Ω
130Ω 130Ω
+3.3V
HIGH
IMPEDANCE
Figure 4. Thevenin Equivalent of Standard PECL Termination
14.5kΩ
V
B
ESD
STRUCTURES
V
B
REF_IN
V
B
= 1.4V
V
CC
V
CC
Figure 6. Simplified REF_IN Pin Circuit Schematic
ESD
STRUCTURES
Qx
V
CC
Qx
Figure 7. Simplified LVPECL Output Circuit Schematic
MAX3625
Qx
150Ω
100Ω
Qx
Z
0
= 50Ω
Z
0
= 50Ω
HIGH
IMPEDANCE
150Ω
0.1μF
NOTE: AC-COUPLING IS OPTIONAL.
0.1μF
Figure 5. AC-Coupled PECL Termination
MAX3625
Low-Jitter, Precision Clock Generator
with Three Outputs
_______________________________________________________________________________________ 9
Layout Considerations
The inputs and outputs are critical paths for the
MAX3625, and care should be taken to minimize dis-
continuities on these transmission lines. Here are some
suggestions for maximizing the MAX3625’s perfor-
mance:
• An uninterrupted ground plane should be posi-
tioned beneath the clock I/Os.
• Supply and ground pin vias should be placed
close to the IC and the input/output interfaces to
allow a return current path to the MAX3625 and the
receive devices.
• Supply decoupling capacitors should be placed
close to the MAX3625 supply pins.
• Maintain 100Ω differential (or 50Ω single-ended)
transmission line impedance out of the MAX3625.
• Use good high-frequency layout techniques and
multilayer boards with an uninterrupted ground
plane to minimize EMI and crosstalk.
Refer to the MAX3625 Evaluation Kit for more information.
Chip Information
TRANSISTOR COUNT: 10,670
PROCESS: BiCMOS
Pin Configuration
P1-P3P4-P6P7-P9P10-P10

MAX3625CUG+T

Mfr. #:
Buy MAX3625CUG+T
Manufacturer:
Microchip / Microsemi
Description:
Clock Generators & Support Products
Lifecycle:
New from this manufacturer.
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