128K x 8 Static RAM
CY7C109BN
CY7C1009BN
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-06430 Rev. ** Revised February 1, 2006
Features
•High speed
—t
AA
= 12 ns
• Low active power
— 495 mW (max. 12 ns)
• Low CMOS standby power
— 55 mW (max.) 4 mW
• 2.0V Data Retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
1
, CE
2
, and OE options
Functional Description
[1]
The CY7C109BN/CY7C1009BN is a high-performance
CMOS static RAM organized as 131,072 words by 8 bits. Easy
memory expansion is provided by an active LOW Chip Enable
(CE
1
), an active HIGH Chip Enable (CE
2
), an active LOW
Output Enable (OE
), and three-state drivers. Writing to the
device is accomplished by taking Chip Enable One (CE
1
) and
Write Enable (WE
) inputs LOW and Chip Enable Two (CE
2
)
input HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is
then written into the location specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable One (CE
1
) and Output Enable (OE) LOW while forcing
Write Enable (WE
) and Chip Enable Two (CE
2
) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY7C109BN is available in standard 400-mil-wide SOJ
and 32-pin TSOP type I packages. The CY7C1009BN is
available in a 300-mil-wide SOJ package. The CY7C1009BN
and CY7C109BN are functionally equivalent in all other
respects.
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
14
15
Logic Block Diagram Pin Configurations
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
CE
2
I/O
1
I/O
2
I/O
3
512x256x8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
11
A
13
A
12
A
A
10
CE
1
A
A
16
A
9
1
2
3
4
5
6
7
8
9
10
11
14
19
20
24
23
22
21
25
28
27
26
Top View
SOJ
12
13
29
32
31
30
16
15
17
18
GND
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
WE
V
CC
A
15
A
13
A
8
A
9
I/O
7
I/O
6
I/O
5
I/O
4
A
2
NC
I/O
0
I/O
1
I/O
2
CE
1
OE
A
10
I/O
3
A
1
A
0
A
11
CE
2
A
6
A
7
A
16
A
14
A
12
WE
V
CC
A
4
A
13
A
8
A
9
OE
TSOP I
Top View
(not to scale)
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O
2
I/O
1
GND
I/O
7
I/O
4
I/O
5
I/O
6
I/O
0
CE
A
11
A
5
17
18
8
9
10
11
12
13
14
15
16
CE
2
A
15
NC
A
10
I/O
3
A
1
A
0
A
3
A
2
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