DATA SHEET
1:8, LVDS Output Fanout Buffer
IDT8SLVD1208I
IDT8SLVD1208NBGI REVISION A MAY 1, 2013 1 ©2013 Integrated Device Technology, Inc.
General Description
The IDT8SLVD1208I is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The
IDT8SLVD1208I is characterized to operate from a 2.5V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the IDT8SLVD1208I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. Two selectable differential inputs and eight low skew
outputs are available. The integrated bias voltage reference enables
easy interfacing of single-ended signals to the device inputs. The
device is optimized for low power consumption and low additive
phase noise.
Features
Eight low skew, low additive jitter LVDS output pairs
Two selectable, differential clock input pairs
Differential PCLK, nPCLK pairs can accept the following
differential input levels: LVDS, LVPECL
Maximum input clock frequency: 2GHz (maximum)
LVCMOS/LVTTL interface levels for the control input (input select)
Output skew: 8ps (typical)
Propagation delay: 255ps (typical)
Low additive phase jitter, RMS; f
REF
= 156.25MHz, V
PP
= 1V,
10kHz - 20MHz: 65fs (typical)
Maximum device current consumption (I
DD
): 170mA
2.5V supply voltage
Lead-free (RoHS 6), 28-Lead VFQFN packaging
-40°C to 85°C ambient operating temperature
Pin Assignment
IDT8SLVD1208I
28 lead VFQFN
5.0mm x 5.0mm x 0.925mm package body
Pad size 3.25mm x 3.25 mm
NB Package
Top View
22
23
24
25
1
2
3
4
14
13
12
11
21
20
19
18
Q4
nQ4
Q5
nQ5
GND
nQ0
Q0
V
REF0
n
Q
7
P
C
L
K
1
n
P
C
L
K
1
V
R
E
F
1
n
Q
3
Q
3
n
Q
2
Q
2
26
27
28
Q6
nQ6
V
DD
5
6
7
G
N
D
Q
7
10
9
8
nPCLK0
PCLK0
V
DD
1
7
1
6
1
5
n
Q
1
Q
1
V
DD
S
E
L
IDT8SLVD1208I Data Sheet 1:8, LVDS OUTPUT FANOUT BUFFER
IDT8SLVD1208NBGI REVISION A MAY 1, 2013 2 ©2013 Integrated Device Technology, Inc.
Block Diagram
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
PCLK1
nPCLK1
VDD
GND
Pullup + Pulldown
Pulldown
SEL
Pullup + Pulldown
0
1
PCLK0
nPCLK0
VDD
GND
Pullup + Pulldown
Pulldown
VDD
GND
Reference
Voltage
Generator
V
REF0
V
REF1
GND
GND
IDT8SLVD1208I Data Sheet 1:8, LVDS OUTPUT FANOUT BUFFER
IDT8SLVD1208NBGI REVISION A MAY 1, 2013 3 ©2013 Integrated Device Technology, Inc.
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
NOTE: Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Function Table
Table 3. SEL Input Selection Function Table
NOTE: SEL is an asynchronous control.
Number Name Type Description
1, 14 GND Power
Ground supply pin.
4 SEL Input
Pullup/
Pulldown
Reference select control pin. See Table 3 for function. LVCMOS/LVTTL
interface levels.
5 PCLK1 Input Pulldown
Non-inverting differential clock/data input.
6 nPCLK1 Input
Pullup/
Pulldown
Inverting differential clock/data input. V
DD
/2 default when left floating.
8, 15, 28 V
DD
Power
Power supply pin.
9 PCLK0 Input Pulldown
Non-inverting differential clock/data input.
10 nPCLK0 Input
Pullup/
Pulldown
Inverting differential clock/data input. V
DD
/2 default when left floating.
11 V
REF0
Output Bias voltage reference for the PCLK0, nPCLK0 inputs.
7V
REF1
Output Bias voltage reference for the PCLK1, nPCLK1 inputs.
12, 13 Q0, nQ0 Output
Differential output pair 0. LVDS interface levels.
16, 17 Q1, nQ1 Output
Differential output pair 1. LVDS interface levels.
18, 19 Q2, nQ2 Output
Differential output pair 2. LVDS interface levels.
20, 21 Q3, nQ3 Output
Differential output pair 3. LVDS interface levels.
22, 23 Q4, nQ4 Output
Differential output pair 4. LVDS interface levels.
24, 25 Q5, nQ5 Output
Differential output pair 5. LVDS interface levels.
26, 27 Q6, nQ6 Output
Differential output pair 6. LVDS interface levels.
2, 3 Q7, nQ7 Output
Differential output pair 7. LVDS interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 2 pF
R
PULLDOWN
Input Pulldown Resistor 51 k
R
PULLUP
Input Pullup Resistor 51 k
Input
OperationSEL
0 PCLK0, nPCLK0 is the selected differential clock input.
1 PCLK1, nPCLK1 is the selected differential clock input.
Open Input buffers are disabled and outputs are static.

8SLVD1208NBGI

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution LOW COST SIGE ARRAY
Lifecycle:
New from this manufacturer.
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