VIPer100A-E/ASP-E 5 Operation Description
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V
DDhyst
is the voltage hysteresis of the UVLO logic (refer to the minimum specified value).
The soft start feature can be implemented on the COMP pin through a simple capacitor which
will be also used as the compensation network. In this case, the regulation loop bandwidth is
rather low, because of the large value of this capacitor. In case a large regulation loop
bandwidth is mandatory, the schematics of (see Figure 17) can be used. It mixes a high
performance compensation network together with a separate high value soft start capacitor.
Both soft start time and regulation loop bandwidth can be adjusted separately.
If the device is intentionally shut down by tying the COMP pin to ground, the device is also
performing start-up cycles, and the V
DD
voltage is oscillating between V
DDon
and V
DDoff
.
This voltage can be used for supplying external functions, provided that their consumption does
not exceed 0.5mA. (see Figure 18) shows a typical application of this function, with a latched
shutdown. Once the "Shutdown" signal has been activated, the device remains in the Off state
until the input voltage is removed.
5.4 Transconductance Error Amplifier
The VIPer100A-E/ASP-E includes a transconductance error amplifier. Transconductance Gm is
the change in output current (I
COMP
) versus change in input voltage (V
DD
). Thus:
The output impedance Z
COMP
at the output of this amplifier (COMP pin) can be defined as:
This last equation shows that the open loop gain A
VOL
can be related to G
m
and Z
COMP
:
A
VOL
= G
m
x Z
COMP
where G
m
value for VIPer100A-E/ASP-E is 1.5 mA/V typically.
G
m
is defined by specification, but Z
COMP
and therefore A
VOL
are subject to large tolerances.
An impedance Z can be connected between the COMP pin and ground in order to define the
transfer function F of the error amplifier more accurately, according to the following equation
(very similar to the one above):
F
(S)
= Gm x Z(S)
The error amplifier frequency response is reported in Figure 10. for different values of a simple
resistance connected on the COMP pin. The unloaded transconductance error amplifier shows
an internal Z
COMP
of about 330KΩ. More complex impedance can be connected on the COMP
pin to achieve different compensation level. A capacitor will provide an integrator function, thus
eliminating the DC static error, and a resistance in series leads to a flat gain at higher
frequency, insuring a correct phase margin. This configuration is illustrated in Figure 20
As shown in Figure 19 an additional noise filtering capacitor of 2.2nF is generally needed to
avoid any high frequency interference.
Is also possible to implement a slope compensation when working in continuous mode with
duty cycle higher than 50%. Figure 21 shows such a configuration. Note: R1 and C2 build the
classical compensation network, and Q1 is injecting the slope compensation with the correct
polarity from the oscillator sawtooth.
G
m
∂l
COMP
∂V
DD
-------------------=
Z
CO MP
∂
V
CO MP
∂
I
COMP
---------------------
1
G
m
--------
∂
V
COMP
∂V
DD
------------------------ -×==
