IR21592/IR21593
(
S
)
&
(
PbF
)
20 www.irf.com
1V
3V
5V
0
0.5V 5V
V
MIN
V
DIM
R
MIN
R
MAX
V
CT
LO
USER
SETTING
DIM
RANGE
ν
0 -90 -180
ΕΕΕ
ν
REF
Figure 14, Dimming interface
The charging time of CT from 1V to 5.1V
determines the on-time of output gate drivers HO
and LO and corresponds to -180 degrees of
possible phase shift in load current (minus
deadtime). For the 0 to -90 degree dim range, the
voltage on pin MIN is bounded between 1V and
3V using pins MIN and MAX. An external resistor
on pin MAX programs the minimum phase shift
reference (maximum lamp power) corresponding
to 5V on pin DIM, and an external resistor on pin
MIN sets the maximum phase shift (minimum
lamp power) corresponding to 0.5V on pin DIM.
Current Sensing
During dimming, the current sensing circuitry
(Figure 15) detects over-current which can occur
during hard-switching (see Fault section), and
zero-crossing to measure the phase of the total
load current. To reject any switching noise which
can occur at the turn-on of the low-side MOSFET
or IGBT, a digital current sense blanking circuit
blanks out the signal from the zero-crossing
detection comparator for 400ns after LO goes 'high'
(Figure 16).
11
12
COM
LO
10
CS
1.6V
Q2
RCS
16
HO
Q2
15
VS
Half
Bridge
Output
I
LOAD
V
BUS
(+)
V
BUS
(-)
Load
Return
Half
Bridge
Driver
IR2159
PHASE
CONTROL
FAULT
LOGIC
400ns
BLANK
R1
Figure 15, Current sensing circuitry.
The internal blank time reduces the dimming range
slightly (Figure 16) when operating at minimum
phase shift (maximum lamp power). The external
programming resistor on pin MAX must be
selected such that the minimum phase shift is
set a safe margin away from the blank time. A
series resistor (R1) is required to limit the amount
of current flowing out of pin CS when the voltage
across RCS goes below -0.7V. A filter capacitor
at pin CS may be required due to other possible
asynchronous noise sources present in the ballast
system.
