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P3I2005AG-08SR

P1-P3P4-P6
© Semiconductor Components Industries, LLC, 2010
June, 2010 − Rev. 1
1 Publication Order Number:
P3I2005A/D
P3I2005A
General Purpose Peak EMI
Reduction IC
Product Description
P3I2005A is a versatile, 3.3 V / 5 V, 1x spread spectrum frequency
modulator designed to reduce electromagnetic interference (EMI) at
the clock source, allowing system wide reduction of EMI of down
stream clock and data dependent signals. The device allows significant
system cost savings by reducing the number of circuit board layers
ferrite beads, shielding and other passive components that are
traditionally required to pass EMI regulations.
P3I2005A modulates the output of a PLL in order to “spread” the
bandwidth of a synthesized clock, and more importantly, decreases the
peak amplitudes of its harmonics. This results in significantly lower
system EMI compared to the typical narrow band signal produced by
oscillators and most frequency generators. Lowering EMI by
increasing a signal’s bandwidth is called ‘spread spectrum clock
generation’.
P3I2005A accepts an input from an external reference clock and
locks to a 1x modulated clock output. Two logic pins S0 and D_C
enable selecting one of the 4 different frequency deviations. Refer
Deviation Selection table. Frequency Range Selection pin enables
operation in one of the two frequency ranges. P3I2005A operates over
a supply voltage range of 5 V / 3.3 V. P3I2005A is available in 8 Pin
SOIC Package.
Features
• 1x, LVCMOS Peak EMI Reduction
• Input Clock Frequency : 10 MHz − 100 MHz
• Output Clock Frequency : 10 MHz − 100 MHz
• Four different Frequency Deviation selection
• Frequency range Selection
• Supply voltage: 5 V $ 0.5 V
3.3 V $ 0.3 V
• 8 Pin SOIC Package
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Application
• P3I2005A is targeted for use in a broad range of notebook and
desktop PCs and consumer electronic applications.
SOIC−8
CASE 751
MARKING
DIAGRAM
http://onsemi.com
PIN CONFIGURATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
VDD
D_C
CLKIN/XIN
1
2
3
4
5
6
7
8
S0
ModOUT
GND
FRS
P3I2005A
XOUT
1
8
AFG = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
AFG
ALYWX
G
1
8
P3I2005A
http://onsemi.com
2
GND
CLKIN/XIN
ModOUT
PLL
FRS
XOUT
D_CS0 VDD
Crystal
Oscillator
Figure 1. Block Diagram
PIN DESCRIPTION
Pin# Pin Name Type Description
1 CLKIN / XIN I External reference Clock input or Crystal connection.
2 XOUT O Crystal connection. If using an external reference, this pin must be left unconnected.
3 D_C I Deviation Selection. Has an internal pull−up resistor. Refer to Deviation Selection table
4 GND P Ground connection.
5 S0 I Deviation Selection. Has an internal pull−up resistor. Refer to Deviation Selection table
6 FRS I Frequency Range Selection. Has an internal pull−up resistor
7 ModOUT O Buffered Modulated Clock Output.
8 VDD P Power supply for the entire chip(3.3 V/5 V)
FREQUENCY RANGE SELECTION TABLE
FRS Frequency(MHz)
0 10 − 30
1 30 − 100
DEVIATION SELECTION TABLE
Deviation (%)
D_C S0
FS = 0 FS = 1
10 MHz 20 MHz 30 MHz 30 MHz 80 MHz 100 MHz
0 0 −4.5 −3.6 −1.7 −4.8 −3.6 −2.6
0 1 −2.6 −2 −1 −2.7 −2 −1.5
1 0 $2.6 $2 $1 $2.75 $2 $1.5
1 1 $1.7 $1.25 $0.7 $1.8 $1.25 $1
P3I2005A
http://onsemi.com
3
OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VDD
(5V)
Supply Voltage 4.5 5.5 V
VDD
(3.3V)
Supply Voltage 3 3.6 V
T
A
Operating Temperature −40 +85 °C
C
L
Load Capacitance 15 pF
C
IN
Input Capacitance 7 pF
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Rating Unit
VDD, V
IN
Voltage on any input pin with respect to Ground −0.5 to +7.0 V
T
STG
Storage temperature −65 to +125 °C
T
s
Max. Soldering Temperature (10 sec) 260 °C
T
J
Junction Temperature 150 °C
T
DV
Static Discharge Voltage
(As per JEDEC STD22− A114−B)
2 kV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may
affect device reliability.
DC ELECTRICAL CHARACTERISTICS FOR V
DD
= 5 V $ 0.5 V
Symbol Parameter Min Typ Max Unit
VDD Operating voltage 4.5 5.0 5.5 V
V
IL
Input low voltage GND
– 0.3
0.8 V
V
IH
Input high voltage 2.0 V
DD
+
0.3
V
I
IL
Input low current 100
mA
I
IH
Input high current 100
mA
V
OL
Output low voltage (I
OL
= 12 mA) 0.4 V
V
OH
Output high voltage (I
OH
= −12 mA) 2.5 V
I
CC
Static supply current (CLKIN/XIN pulled to GND) 12 mA
I
DD
Dynamic supply current (Unloaded Output)
FS = 0 (@ 30 MHz) 34
mA
FS = 1 (@ 100 MHz) 40
Z
OUT
Output impedance 30
W
P1-P3P4-P6

P3I2005AG-08SR

Mfr. #:
Buy P3I2005AG-08SR
Manufacturer:
ON Semiconductor
Description:
Phase Locked Loops - PLL 10-100MHZ 5V/3V GP EMI
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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