IDT
®
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock 1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
22
Byte 18 Differential Output Control Register
Bit
Name
Description
RW
0
1
Default
7
SRC10_STP_CRTL If set, SRC10 stops with PCI_STOP# RW Free Running
Stops with PCI_STOP#
assertion
0
6
SRC11_STP_CRTL If set, SRC11 stops with PCI_STOP# RW Free Running
Stops with PCI_STOP#
assertion
0
5
SRC/CPUITP_SRC8 IO_VOUT2
SRC & CPUITP_SRC8 IO Output Voltage Select (Most Significant
Bit)
RW 1
4
SRC/CPUITP_SRC8 IO_VOUT1
SRC IO & CPUITP_SRC8 Output Voltage Select
RW
0
3
SRC/CPUITP_SRC8 IO_VOUT0
SRC & CPUITP_SRC8 IO Output Voltage Select (Least
Significant Bit)
RW 1
2
SATA/SRC2 IO_VOUT2
SATA_SRC2 IO Output Voltage Select (Most Significant Bit)
RW
1
1
SATA/SRC2 IO_VOUT1
SATA_SRC2 IO Output Voltage Select
RW
0
0
SATA/SRC2 IO_VOUT0 SATA_SRC2 IO Output Voltage Select (Least Significant Bit) RW 1
Byte 19 Differential Output Control Register
Bit
Name
Description
RW
0
1
Default
7
LCD_SS (SRC1) IO_VOUT2
LCD_SS IO Output Voltage Select (Most Significant Bit)
RW
1
6
LCD_SS (SRC1) IO_VOUT1
LCD_SS IO Output Voltage Select
RW
0
5
LCD_SS (SRC1) IO_VOUT0
LCD_SS IO Output Voltage Select (Least Significant Bit)
RW
1
4
SRC0/DOT96 IO_VOUT2 SRC0_DOT96 IO Output Voltage Select (Most Significant Bit) RW 1
3
SRC0/DOT96 IO_VOUT1
SRC0_DOT96 IO Output Voltage Select
RW
0
2
SRC0/DOT96 IO_VOUT0 SRC0_DOT96 IO Output Voltage Select (Least Significant Bit) RW 1
1
Reserved
Reserved
RW
-
-
0
0
Reserved
Reserved
RW
-
-
0
Byte 20 Single Ended Slew Rate Control Register
Bit Name Description Type 0 1 Default
7
48MHz
RW 00 = Hi-Z 01 = 1.4 V/ns 0
6
48MHz
RW 10 = 2.0 V/ns 11 = 2.4 V/ns 1
5
PCIF5
RW 00 = Hi-Z 01 = 1.4 V/ns 0
4
PCIF5
RW 10 = 2.0 V/ns 11 = 2.4 V/ns 1
3
PCI4
RW
00 = Hi-Z 01 = 1.4 V/ns 0
2
PCI4
RW
10 = 2.0 V/ns 11 = 2.4 V/ns
1
1
PCI3
RW 00 = Hi-Z 01 = 1.4 V/ns 0
0
PCI3
RW 10 = 2.0 V/ns 11 = 2.4 V/ns 1
Byte 21 Single Ended Slew Rate & M/N Enable Control Register
Bit Name Description Type 0 1 Default
7
PCI2
RW 00 = Hi-Z 01 = 1.4 V/ns 0
6
PCI2
RW 10 = 2.0 V/ns 11 = 2.4 V/ns 1
5
PCI1
RW 00 = Hi-Z 01 = 1.4 V/ns 0
4
PCI1
RW 10 = 2.0 V/ns 11 = 2.4 V/ns 1
3
PCI0
RW 00 = Hi-Z 01 = 1.4 V/ns 0
2
PCI0
RW 10 = 2.0 V/ns 11 = 2.4 V/ns 1
1
Reserved
Reserved
RW
-
-
0
0
Reserved
Reserved
RW
-
-
0
See Table 3: V_IO Selection
(Default is 0.8V)
Slew Rate Control
Slew Rate Control
Slew Rate Control
See Table 3: V_IO Selection
(Default is 0.8V)
See Table 3: V_IO Selection
(Default is 0.8V)
See Table 3: V_IO Selection
(Default is 0.8V)
Slew Rate Control
Slew Rate Control
Slew Rate Control
Slew Rate Control
IDT
®
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock 1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
23
Test Clarification Table
Comments
FSLC/
TEST_SEL
HW PIN
FSLB/
TEST_MODE
HW PIN
TEST ENTRY
BIT
B9b3
REF/N or
HI-Z
B9b4
OUTPUT
<2.0V X 0 0 NORMAL
>2.0V 0 X 0 HI-Z
>2.0V 0 X 1 REF/N
>2.0V 1 X 0 REF/N
>2.0V 1 X 1 REF/N
<2.0V X 1 0 HI-Z
<2.0V X 1 1 REF/N
B9b3: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
B9b4: 1= REF/N, Default = 0 (HI-Z)
HW
SW
CK_PWRG=1 w/ TEST_SEL = 1 to enter test mode
Cycle power to disable test mode
FSLC./TEST_SEL -->3-level latched input
If CK_PWRG=1 w/ V>2.0V then use TEST_SEL
If CK_PWRG=1 w/ V<2.0V then use FSLC
FSLB/TEST_MODE -->low Vth input
TEST_MODE is a real time input
If TEST_SEL HW pin is 0 after CK_PWRG=1,
test mode can be invoked through B9b3.
If test mode is invoked by B9b3, only B9b4
is used to select HI-Z or REF/N
FSLB/TEST_Mode pin is not used.
Cycle power to disable test mode, one shot control
IDT
®
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock 1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
24

9ERS3165BGLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner EMBEDDED CK505 COMPATIBLE CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
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