16
FN8197.1
April 26, 2006
HIGH-VOLTAGE WRITE CYCLE TIMING
XDCP TIMING
Note: (8) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling
edge of SCL.
TIMING DIAGRAMS
START and STOP Timing
Input Timing
Output Timing
Symbol Parameter Typ. Max. Unit
t
WR
High-voltage write cycle time (store instructions) 5 10 ms
Symbol Parameter Min. Max. Unit
t
WRPO
Wiper response time after the third (last) power supply is stable 10 µs
t
WRL
Wiper response time after instruction issued (all load instructions) 10 µs
t
WRID
Wiper response time from an active SCL/SCK edge (increment/decrement instruction) 10 µs
t
SU:STA
t
HD:STA
t
SU:STO
SCL
SDA
t
R
(START) (STOP)
t
F
t
R
t
F
SCL
SDA
t
HIGH
t
LOW
t
CYC
t
HD:DAT
t
SU:DAT
t
BUF
SCL
SDA
t
DH
t
AA
X9428
17
FN8197.1
April 26, 2006
XDCP Timing (for All Load Instructions)
XDCP Timing (for Increment/Decrement Instruction)
Write Protect and Device Address Pins Timing
SCL
SDA
V
W
/R
W
(STOP)
LSB
t
WRL
SCL
SDA
V
W
/R
W
t
WRID
Wiper Register Address Inc/Dec Inc/Dec
SDA
SCL
...
...
...
WP
A0, A2, A3
t
SU:WPA
t
HD:WPA
(START) (STOP)
(Any Instruction)
X9428
18
FN8197.1
April 26, 2006
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
Application Circuits
V
R
V
W
/R
W
+V
R
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Noninverting Amplifier Voltage Regulator
Offset Voltage Adjustment Comparator with Hysteresis
+
V
S
V
O
R
2
R
1
V
O
= (1+R
2
/R
1
)V
S
R
1
R
2
I
adj
V
O
(REG) = 1.25V (1+R
2
/R
1
)+I
adj
R
2
V
O
(REG)V
IN
317
+
V
S
V
O
R
2
R
1
V
UL
= {R
1
/(R
1
+R
2
)} V
O
(max)
V
LL
= {R
1
/(R
1
+R
2
)} V
O
(min)
100kΩ
10kΩ10kΩ
10kΩ
-12V+12V
TL072
+
V
S
V
O
R
2
R
1
}
}
X9428

X9428YS16ZT1

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs SINGLE XDCP 2KOHM 64 TAP 2-WIRE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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