7
FN8197.1
April 26, 2006
Figure 3. Two-Byte Instruction Sequence
The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9428 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse
(t
HIGH
) while SDA is HIGH, the selected wiper will
move one resistor segment towards the V
H
/R
H
terminal. Similarly, for each SCL clock pulse while
SDA is LOW, the selected wiper will move one resistor
segment towards the V
L
/R
L
terminal. A detailed
illustration of the sequence and timing for this
operation are shown in Figures 5 and 6 respectively.
Table 1. Instruction Set
Note: (7) 1/0 = data is one or zero
S
T
A
R
T
0101A3A20A0A
C
K
I3 I2 I1 I0 R1 R0 0 0 A
C
K
SCL
SDA
S
T
O
P
Instruction
Instruction Set
OperationI
3
I
2
I
1
I
0
R
1
R
0
X
1
X
0
Read Wiper Counter
Register
1 0 0 1 0 0 0 0 Read the contents of the Wiper Counter Register
Write Wiper Counter
Register
1 0 1 0 0 0 0 0 Write new value to the Wiper Counter Register
Read Data Register 1 0 1 1 1/0 1/0 0 0 Read the contents of the Data Register pointed to by
R
1
- R
0
Write Data Register 1 1 0 0 1/0 1/0 0 0 Write new value to the Data Register pointed to by
R
1
- R
0
XFR Data Register to
Wiper Counter Register
1 1 0 1 1/0 1/0 0 0 Transfer the contents of the Data Register pointed to
by R
1
- R
0
to its Wiper Counter Register
XFR Wiper Counter
Register to Data Register
1 1 1 0 1/0 1/0 0 0 Transfer the contents of the Wiper Counter Register
to the Data Register pointed to by R
1
- R
0
Increment/Decrement
Wiper Counter Register
0 0 1 0 0 0 0 1/0 Enable Increment/decrement of the Wiper Counter
Register
X9428
8
FN8197.1
April 26, 2006
Figure 4. Three-Byte Instruction Sequence
Figure 5. Increment/Decrement Instruction Sequence
Figure 6. Increment/Decrement Timing Limits
S
T
A
R
T
0 1 0 1 A3 A2 0 A0 A
C
K
I3 I2 I1 I0 R1 R0 0 0 A
C
K
SCL
SDA
S
T
O
P
A
C
K
0 0 D5 D4 D3 D2 D1 D0
S
T
A
R
T
0101A3A20A0A
C
K
I3 I2 I1 I0 R0 0 0 A
C
K
SCL
SDA
S
T
O
P
XX
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
R1
SCL
SDA
V
W
/R
W
INC/DEC
CMD
Issued
Voltage Out
t
WRID
X9428
9
FN8197.1
April 26, 2006
Figure 7. Acknowledge Response from Receiver
Figure 8. Detailed Potentiometer Block Diagram
SCL from
Data Output
from Transmitter
1
89
START
Acknowledge
Master
Data Output
from Receiver
Serial Data Path
From Interface
Circuitry
Register 0 Register 1
Register 2 Register 3
Serial
Bus
Input
Parallel
Bus
Input
Wiper
Counter
Register
INC/DEC
Logic
UP/DN
CLK
Modified SCL
UP/DN
V
H
/R
H
V
L
/R
L
V
W
/R
W
If WCR = 00[H] then V
W
/R
W
= V
L
/R
L
If WCR = 3F[H] then V
W
/R
W
= V
H
/R
H
8 6
C
o
u
n
t
e
r
D
e
c
o
d
e
(WCR)
X9428

X9428WV14IZ-2.7

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC DGTL POT 10K 1CH 14TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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