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whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction
with mission-critical equipment or applications. Any performance specifi cations are believed to be reliable but are not verifi ed, and Buyer must conduct and complete all performance and other testing of the products, alone
and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifi cations or parameters provided by Microsemi. It is the Buyer’s responsibility to independently determine suitability
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Highlights
• IEEE 1588v2 compliant
• 128/256-bit MACsec support
• RXAUI/XAUI support
• SFP+ I/O with KR support
• 1 GbE support
Applications
• Multiple-port RXAUI/XAUI to
• SFI/ SFP+ line cards or NICs
• 10GBASE-KR compliant backplane
transceivers
• Carrier Ethernet networks requiring IEEE
1588v2 timing
• Secure data center-to-data center
interconnects
• 10 GbE switch cards, router cards, and
NICs
Microsemi’s 10G/1G SerDes PHY provides MACsec, IEEE 1588v2, and
hardware-based KR support for timing-critical applications, including all
industry-standard protocol encapsulations.
The VSC8491 device offers a seamless integration between IEEE 1588v2
and the MACsec engine with no loss of precision. It also includes one serial
port routed to one or both of the RXAUI/XAUI interfaces using the integrated
crosspoint.
VeriTime™ is Microsemi's patent-pending timing technology that delivers the
industry’s most accurate IEEE 1588v2 timing implementation. IEEE1588v2
timing integrated in the PHY is the quickest, lowest cost method of
implementing the timing accuracy that is critical to maintaining existing
timing-critical capabilities during the migration from TDM to packet-based
architectures.
The VSC8491 device supports 1-step and 2-step PTP frames for ordinary
clock, boundary clock, and transparent clock applications, along with
complete Y.1731 OAM performance monitoring capabilities.
MACsec (IEEE 802.1AE) defi nes a set of protocols to meet the security
requirements for protecting data traversing Ethernet LANs, such as input
classifi cation, frame encryption/decryption, and performance and latency
monitoring.
The VSC8491 device meets the SFP+ SR/LR/ER/ZR/220MMF host
requirements in accordance with the SFF-8431 specifi cations. It also
compensates for optical impairments in SFP+ applications, along with
degradations of the PCB. The VSC8491 device provides full KR support,
including KR state machine, for autonegotiation and link optimization. The
transmit path incorporates a multitap output driver to provide fl exibility
to meet the demanding 10GBASE-KR (IEEE 802.3ap) Tx output launch
requirements.
A complete suite of BIST functionality includes line and client loopbacks
along with pattern generation and error detection. Highly fl exible clocking
options support LAN and WAN operation using single 156.25 MHz reference
clock rate inputs for seamless Synchronous Ethernet support. The VSC8491
device includes a failover switching capability for protection routing, along
with selectable lane ordering.
VSC8491
WAN/LAN/Backplane RXAUI/XAUI to SFP+/KR 10 GbE SerDes PHY with VeriTime™ and MACsec
Switch Module
Dual
10 GbE
MAC/NIC
10 GbE Line Card or NIC
VSC8491
10GBASE-KR
Backplane
1 × 10G
1 × 1G
RXAUI/XAUI
10 GbE
RXAUI/
XAUI
Switch
Module
2/4
2/4
1 × 10G/
1 × 1G
RXAUI/
XAUI
2/4
2/4
VSC8491