ICL232
5
FN3020.8
October 15, 2014
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Detailed Description
The ICL232 is a dual RS-232 transmitter/receiver powered by a
single +5V power supply which meets all ElA RS232C
specifications and features low power consumption. Figure 1
illustrates the major elements of the ICL232. The circuit is divided
into three sections: a voltage doubler/inverter, dual transmitters,
and dual receivers.
Voltage Converter
An equivalent circuit of the dual charge pump is illustrated in
Figure 6
.
The voltage quadrupler contains two charge pumps which use two
phases of an internally generated clock to generate +10V and
-10V. The nominal clock frequency is 16kHz. During phase one of
the clock, capacitor C1 is charged to V
CC
. During phase two, the
voltage on C1 is added to V
CC
, producing a signal across C2 equal
to twice V
CC
. At the same time, C3 is also charged to 2V
CC
, and
then during phase one, it is inverted with respect to ground to
produce a signal across C4 equal to -2V
CC
. The voltage converter
accepts input voltages up to 5.5V. The output impedance of the
doubler (V+) is approximately 200Ω, and the output impedance of
the inverter (V-) is approximately 450Ω . Typical graphs are
presented which show the voltage converters output vs input
voltage and output voltages vs load characteristics. The test circuit
(Figure 2
) uses 1µF capacitors for C1 to C4, however, the value is
not critical. Increasing the values of C1 and C2 will lower the
output impedance of the voltage doubler and inverter, and
increasing the values of the reservoir capacitors, C3 and C4,
lowers the ripple on the V+ and V- supplies.
Transmitters
The transmitters are TTL/CMOS compatible inverters which
translate the inputs to RS-232 outputs. The input logic threshold is
about 26% of V
CC
, or 1.3V for V
CC
= 5V. A logic 1 at the input
results in a voltage of between -5V and V- at the output, and a logic
0 results in a voltage between +5V and (V+ - 0.6V). Each
transmitter input has an internal 400kΩ pullup resistor so any
unused input can be left unconnected and its output remains in its
low state. The output voltage swing meets the RS-232C
specification of 5V minimum with the worst case conditions of:
both transmitters driving 3kΩ minimum load impedance,
V
CC
= 4.5V, and maximum allowable operating temperature. The
transmitters have an internally limited output slew rate which is
less than 30V/µs. The outputs are short circuit protected and can
be shorted to ground indefinitely. The powered down output
impedance is a minimum of 300Ω with 2V applied to the outputs
and V
CC
= 0V.
Receivers
The receiver inputs accept up to 30V while presenting the
required 3kΩ to 7kΩ input impedance even it the power is off
(V
CC
= 0V). The receivers have a typical input threshold of 1.3V
which is within the 3V limits, known as the transition region, of
the RS-232 specification. The receiver output is 0V to V
CC
. The
output will be low whenever the input is greater than 2.4V and
high whenever the input is floating or driven between +0.8V and
-30V. The receivers feature 0.5V hysteresis to improve noise
rejection.
Applications
The ICL232 may be used for all RS-232 data terminal and
communication links. It is particularly useful in applications
where 12V power supplies are not available for conventional
RS-232 interface circuits. The applications presented represent
typical interface configurations.
A simple duplex RS-232 port with CTS/RTS handshaking is
illustrated in Figure 11
. Fixed output signals such as DTR (data
terminal ready) and DSRS (data signaling rate select) is
generated by driving them through a 5kΩ resistor connected to
V+.
T1
IN
, T2
IN
T1
OUT
, T2
OUT
V
OH
V
OL
t
r
t
f
90%
10%
Instantaneous
Slew Rate (SR)
=
(0.8) (V
OH
- V
OL
)
t
r
or
(0.8) (V
OL
- V
OH
)
t
f
FIGURE 7. SLEW RATE DEFINITION
T
OUT
V- < V
TOUT
< V+
300Ω
400kΩ
T
XIN
GND < T
XIN
< V
CC
V-
V+
V
CC
FIGURE 8. TRANSMITTER
R
OUT
GND < V
ROUT
< V
CC
5kΩ
R
XIN
-30V < R
XIN
< +30V
GND
V
CC
FIGURE 9. RECEIVER
T1
IN
, T2
IN
V
OH
V
OL
t
PLH
t
PHL
Average Propagation Delay =
t
PHL +
t
PLH
2
OR
R1
IN
, R2
IN
T1
OUT
, T2
OUT
OR
R1
OUT
, R2
OUT
FIGURE 10. PROPAGATION DELAY DEFINITION
