PCA9553_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 29 December 2008 8 of 26
NXP Semiconductors
PCA9553
4-bit I
2
C-bus LED driver with programmable blink rates
7.4 Pins used as general purpose I/Os
LED pins not used to control LEDs can be used as general purpose I/Os.
For use as input: Set LEDn to high-impedance (01) and then read the pin state via the
Input register.
For use as output: Connect external pull-up resistor to the pin and size it according to the
DC recommended operating characteristics. LED output pin is HIGH when the output is
programmed as high-impedance, and LOW when the output is programmed LOW through
the ‘LED selector’ register. The output can be pulse-width controlled when PWM0 or
PWM1 are used.
7.5 Power-on reset
When power is applied to V
DD
, an internal Power-On Reset (POR) holds the PCA9553 in
a reset condition until V
DD
has reached V
POR
. At that point, the reset condition is released
and the PCA9553 registers are initialized to their default states, with all outputs in the OFF
state. Thereafter, V
DD
must be lowered below 0.2 V to reset the device.
8. Characteristics of the I
2
C-bus
The I
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 8).
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 9).
Fig 8. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
