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S-93C86BD4I-T8T1U

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36
3-WIRE SERIAL E
2
PROM
S-93C86B
Rev.5.0
_00
Seiko Instruments Inc.
10
3. Reading (READ)
The READ instruction reads data from a specified address.
After CS has gone high, input an instruction in the order of the start bit, read instruction, and address. Since the
last input address (A
0
) has been latched, the output status of the DO pin changes from high impedance (High-Z) to
low, which is held until the next rise of SK. 16-bit data starts to be output in synchronization with the next rise of
SK.
3. 1 Sequential read
After the 16-bit data at the specified address has been output, inputting SK while CS is high automatically
increments the address, and causes the 16-bit data at the next address to be output sequentially. The
above method makes it possible to read the data in the whole memory space. The last address (A
9
yyy A
1
A
0
= 1 yyy 1 1) rolls over to the top address (A
9
yyy A
1
A
0
= 0 yyy 0 0).
SK
D
13
D
15
0
D
14
D
14
D
13
D
0
D
1
D
2
D
15
D
14
D
0
D
1
D
2
D
13
D
15
43 42 45 46 44
30 29 28 27 26
A
5
A
6
A
7
A
2
A
3
A
4
DI
13
11 10
9 8 7 6 5 4 3 2 1
12
CS
DO
A
8
47
31
14
High-Z
ADRINC
High-Z
0 1 <1>
ADRINC
A
9
A
0
A
1
15 16
Figure 5 Read Timing
3-WIRE SERIAL E
2
PROM
Rev.5.0
_00
S-93C86B
Seiko Instruments Inc.
11
4. Writing (WRITE, ERASE, WRAL, ERAL)
A write operation includes four write instructions: data write (WRITE), data erase (ERASE), chip write (WRAL), and
chip erase (ERAL).
A write instruction (WRITE, ERASE, WRAL, ERAL) starts a write operation to the memory cell when a low level is
input to CS after a specified number of clocks have been input. The SK and DI inputs are invalid during the write
period, so do not input an instruction.
Input an instruction while the output status of the DO pin is high or high impedance (High-Z).
A write operation is valid only in program enable mode (refer to “5. Write enable (EWEN) and write disable
(EWDS)”).
4. 1 Verify operation
A write operation executed by any instruction is completed within 4 ms (write time t
PR
: typically 2 ms), so if the
completion of the write operation is recognized, the write cycle can be minimized. A sequential operation to
confirm the status of a write operation is called a verify operation.
4. 1. 1 Operation
After the write operation has started (CS = low), the status of the write operation can be verified by
confirming the output status of the DO pin by inputting a high level to CS again. This sequence is
called a verify operation, and the period that a high level is input to the CS pin after the write operation
has started is called the verify operation period.
The relationship between the output status of the DO pin and the write operation during the verify
operation period is as follows.
• DO pin = low: Writing in progress (busy)
• DO pin = high: Writing completed (ready)
4. 1. 2 Operation example
There are two methods to perform a verify operation: Waiting for a change in the output status of the
DO pin while keeping CS high, or suspending the verify operation (CS = low) once and then performing
it again to verify the output status of the DO pin. The latter method allows the CPU to perform other
processing during the wait period, allowing an efficient system to be designed.
Caution 1. Input a low level to the DI pin during a verify operation.
2. If a high level is input to the DI pin at the rise of SK when the output status of the DO pin is
high, the S-93C86B latches the instruction assuming that a start bit has been input. In this
case, note that the DO pin immediately enters a high-impedance (High-Z) state.
3-WIRE SERIAL E
2
PROM
S-93C86B
Rev.5.0
_00
Seiko Instruments Inc.
12
4. 2 Writing data (WRITE)
To write 16-bit data to a specified address, change CS to high and then input the WRITE instruction, address,
and 16-bit data following the start bit. The write operation starts when CS goes low. There is no need to
set the data to 1 before writing. When the clocks more than the specified number have been input, the clock
pulse monitoring circuit cancels the WRITE instruction. For details of the clock pulse monitoring circuit, refer
to “ Function to Protect Against Write due to Erroneous Instruction Recognition”.
A9
D15
<1>
1 2 3 4 5 6 7 8 9 10 11
0
1
A8 A7 A6 A5 A4 A3 A2
CS
SK
DI
DO
High-Z
ready
busy
t
PR
t
SV
t
CDS
2914
D0
High-Z
Verify
Standby
t
HZ1
12 13
A1
A0
Figure 6 Data Write Timing
4. 3 Erasing data (ERASE)
To erase 16-bit data at a specified address, set all 16 bits of the data to 1, change CS to high, and then input
the ERASE instruction and address following the start bit. There is no need to input data. The data erase
operation starts when CS goes low. When the clocks more than the specified number have been input, the
clock pulse monitoring circuit cancels the ERASE instruction. For details of the clock pulse monitoring
circuit, refer to “ Function to Protect Against Write due to Erroneous Instruction Recognition”.
SK
DI
<1>
A8 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9
CS
DO
High-Z
11
ready
t
CDS
t
SV
High-Z
t
HZ1
t
PR
A1
A0
12 13
busy
Verify
Standby
A3 A2
10 11
A9
Figure 7 Data Erase Timing
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36

S-93C86BD4I-T8T1U

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Buy S-93C86BD4I-T8T1U
Manufacturer:
ABLIC
Description:
EEPROM EEPROM 16Kb 3 wire
Lifecycle:
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