PL686-35OC-R Datasheet PL686-35OC-R, PL686-35OC, PL686-35DC | P1-P3

(Preliminary) PL686-35

Low Phase Noise, LVPECL XO (for 120MHz to 170MHz 3

rd

Overtone Crystals)

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474- 1000 • www.micrel.com Rev 2/3/12 Page 1

FEATURES

 Advanced non multiplier XO Design for High

Performance Crystal Oscillators

 Input/Output Range: 120MHz to 170MHz

 Uses external resistor for 3

rd

overtone selection

 Ultra Low Phase Noise: -80dBc @10Hz at

156.25MHz

 Ultra Low Phase Jitter: <60fs RMS

 Complementary LVPECL Outputs

 Power Supply: 3.3V ±10%

 Available in Die or Wafer Form

DESCRIPTION

The PL686-35 is a non-multiplier XO IC specifically

designed for 3

rd

overtone crystals from 120MHz to

170MHz. The phase noise performance, with <60fs

phase jitter, makes this an ideal solution for all high

end clocking applications such as SONET, WiMax,

CPRI, OBSAI, Fiber Channel, and any application

where performance and quality are required.

DIE SPECIFICATIONS

Name

Value

Size

952 micron x 952 micron

Reverse side

GND

Pad dimensions

80 micron x 80 micron

Thickness

8 mil

DIE CONFIGURATION

OUTPUT ENABLE LOGIC

OE State* (Pad 4)

Output Buffers State

0

Outputs Tri-Stated

1 (Default)

Outputs Enabled

* Internal 60KΩ pull-up resistor

BLOCK DIAGRAM

Xtal

Osc

XIN

Q

OE

XOUT

QB

Rext

(0,0)

0.952mm

Q

VSS

VDD

XIN

OE

DNC

0.952mm

Die ID

7

8

1

2

3

4

5

6

QB

XOUT

(Preliminary) PL686-35

Low Phase Noise, LVPECL XO (for 120MHz to 170MHz 3

rd

Overtone Crystals)

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474- 1000 • www.micrel.com Rev 2/3/12 Page 2

PAD ASSIGNMENT

Pad #

Name

X (m)*

Y (m)*

Description

1

DNC

-194

-365

Do Not Connect

2

OE

373

-373

Output enable pin. Internal pull up resistor.

3

VSS

373

-127

GND connection

4

Q

315

75

LVPECL output

5

QB

140

315

Complementary LVPECL output

6

VDD

-117

329

V

DD

connection

7

XIN

-372

158

Crystal input connection

8

XOUT

-372

-190

Crystal output connection

* Note: Referenced to center of the die.

ELECTRICAL SPECIFICATIONS

1. Absolute Maximum Ratings

PARAMETERS

SYMBOL

MIN.

MAX.

UNITS

Supply Voltage

V

DD

4.6

V

Input Voltage, DC

V

I

V

SS

-0.5

V

DD

+0.5

V

Output Voltage, DC

V

O

V

SS

-0.5

V

DD

+0.5

V

Storage Temperature

T

S

-65

150

C

Ambient Operating Temperature

T

A

-40

85

C

HBM ESD Protection

2,000

V

Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the

devic e and affect product reliability. These conditions represent a stress rating only, and functional operations of the dev ice at these or any other

conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to

commercial grade only.

(Preliminary) PL686-35

Low Phase Noise, LVPECL XO (for 120MHz to 170MHz 3

rd

Overtone Crystals)

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474- 1000 • www.micrel.com Rev 2/3/12 Page 3

2. Crystal Specifications

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Crystal Resonator Frequency

F

XIN

3

rd

Overtone, AT cut

120

170

MHz

Crystal Loading Rating

C

L (xtal)

5

pF

External Resistor

R

EXT

For 156.25MHz

Connect between XIN and

XOUT.

2200

Ω

Shunt Capacitance

C

0

2.5

pF

Recommended ESR

R

E

C

0

 2.5pF, R

EXT

= 2.2KΩ

30

Ω

C

0

 2.0pF, R

EXT

= 2.2KΩ

40

Ω

3. General Electrical Specifications

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Supply Current

I

DD

Standard LVPECL Loading

(See LVPECL Levels Test Circuit, page 4)

50

mA

Operating Voltage

V

DD

2.97

3.3

3.63

V

Output Clock Duty Cycle

@ V

DD

– 1.3V

(See LVPECL Transition Time Waveform, page 4)

45

50

55

%

Short Circuit Current

50

mA

4. Jitter Specifications

PARAMETERS

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Period Jitter RMS

At 156.25MHz, with capacitive

decoupling between V

DD

and

GND. Over 10,000 cycles

2.3

ps

Period Jitter pk-to-pk

18

Integrated Jitter RMS at 156.25MHz

Integrated 12 kHz to 20 MHz

55

fs

5. Phase Noise Specifications

PARAMETERS

FREQUENCY

@10Hz

@100Hz

@1kHz

@10kHz

@100kHz

@1MHz

@10MHz

UNITS

Phase Noise,

relative to carrier

156.25MHz

-80

-112

-140

-152

-157

-159

-162

dBc/Hz

PL686-35OC-R

PL686-35OC-R

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