CPC7508BTR Datasheet CPC7508BTR, CPC7508B | P10-P12

CPC7508

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means to test the drop without the loading effects of

the line feed circuitry.

• Test_IN Monitor. Break switches SW1 and SW2

plus the TEST_IN switches SW5 and SW6 closed,

all other switches open. With this state it is possible

to monitor the SLIC output while the SLIC is driving

the line.

• Test_OUT Monitor. Break switches SW1 and SW2

plus the TEST_OUT switches SW3 and SW4

closed, all other switches open. With this state it is

possible to monitor the LCAS output while the SLIC

is driving the line.

• Test_IN & OUT. TEST_IN switches SW5 and SW6

plus the TEST_OUT switches SW3 and SW4

closed, all other switches open. This state allows

simultaneous testing of the transmission channel

and the drop.

• Test_IN BRIDGE. TEST_IN switches SW5 and

SW6 plus TEST BRIDGE switches SW7 and SW8

closed, all other switches open. This state allows

connecting the SLIC output to the Test Out bus to

compare the on-hook TEST_OUT Monitor

evaluation. This makes it possible to determine if

there is a failure with the Break Switches.

• All-Off. All switches open. Activation of this state can

be accomplished by setting the appropriate IN

pattern or by pulling the T

input/output low.

2.3 Switch Logic and Control

2.3.1 Introduction

The CPC7508 uses a three input transparent latch as

the interface between the externally controlled inputs,

, IN

and IN

and the switch logic. Control of the

transparent latch is by means of the LATCH input.

Data output from the latch is fed into the switch control

logic which decodes the inputs and drives the

appropriate switches. To prevent undesirable switch

activity during both start-up and power down the

switch control logic also contains under voltage lock

out detection circuitry to manage the behavior of the

CPC7508. The under voltage lock out release

threshold is internally set to ensure all internal logic is

properly biased before accepting external switch

commands from the INx inputs to control the switch

states. Prior to release of the under voltage lock out,

the switch control logic is conditioned to the All-Off

state

2.3.2 Under Voltage Detection and Switch Lock Out

Under voltage detection circuitry in the CPC7508

consists of an internal detector to evaluate the V

supply and smart logic to provide for switch state

control during both power up and power loss

transitions.

Any time an unsatisfactory condition causes the V

supply to fall below the internally set under voltage

lockout threshold, the smart logic overrides user

switch control by blocking the information at the INx

input pins and conditions the switch control logic to

place the switches into the All-Off state.

2.3.2.1 Power Up Sequence

Upon power up, the under voltage detector and smart

logic become active before the switch driver circuits

and the switch control logic can activate any of the

switches. As the V

supply starts up, the rising

supply voltage is evaluated by the under voltage

detector to determine when to de-assert the under

voltage switch lock out command. Prior to release of

the lock out command, the smart logic preconditions

the switch control logic for the All-Off state.

The All_Off state is sustained by holding the LATCH

input at a logic high level. This is accomplished by an

external resistor at the LATCH pin which pulls the

input to the supply voltage used by the on-board logic.

The LATCH logic high secures the switch control logic

and the CPC7508 remains in the All-Off state until the

LATCH input is pulled down to a logic low. Prior to the

assertion of a logic low at the LATCH pin, the control

inputs IN

, IN

and IN

must be properly conditioned.

2.3.2.2 Hot Plug and Power Up Circuit Design

Considerations

To facilitate hot plug insertion and power up control the

LATCH pin has an external pull up resistor to the local

logic power rail that will hold a non-driven LATCH pin

at a logic high state. This enables board designers to

use the CPC7508 with FPGAs and other devices that

provide high impedance outputs during power up and

configuration.

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There are six possible start up scenarios that can

occur during power up. They are:

1. All inputs defined at power up & LATCH = 0

2. All inputs defined at power up & LATCH = 1

3. All inputs defined at power up & LATCH = Z

4. All inputs not defined at power up & LATCH = 0

5. All inputs not defined at power up & LATCH = 1

6. All inputs not defined at power up & LATCH = Z

Under all of the start up situations listed above the

CPC7508 will hold all of it’s switches in the all-off state

during power up. When V

requirements have been

satisfied the LCAS will complete it’s start up procedure

in one of three conditions.

For start up scenario 1 the CPC7508 will transition

from the all-off state to the state defined by the inputs

when V

is valid.

For start up scenarios 2, 3, 5, and 6 the CPC7508 will

power up in the all-off state and remain there until the

LATCH pin is pulled low. This allows for an indefinite

all-off state for boards inserted into a powered system

but are not configured for service or boards that need

to wait for other devices to be configured first.

Start up scenario 4 will start up with all switches in the

all-off state but upon the acceptance of a valid V

the

LCAS will revert to one of the legitimate states listed in

the truth tables and there after may randomly change

states based on input pin leakage currents and

loading. Because the LCAS state after power up can

not be predicted with this start up condition it should

never be utilized.

On designs that do not wish to individually control the

LATCH pins of multi-port cards it is possible to bus

many (or all) of the LATCH pins together to create a

single board level input enable control.

2.3.2.3 Power Loss Sequence

For a falling V

event, the under voltage lock out

detector monitors the supply voltage and upon

reaching the internally set threshold point asserts the

under voltage lock out command. This feature protects

the integrity of the application during power dropouts

by assuring proper logic and switch behavior up to the

moment the switches are forced off and external

inputs are suppressed. Upon assertion of the under

voltage lock out command the switch control logic is

conditioned into the All_Off state where it will remain

until V

recovers and the LATCH input is pulled low.

2.3.3 Data Latch

The CPC7508 has an integrated transparent data

latch controlled by the LATCH input which can be used

as an enable or a chip select function when the INx

inputs of multiple LCAS devices are connected to

common busses. The latch enable operation is

controlled by TTL input logic levels at the LATCH pin.

Control data is input to the latch via the input pins IN

and IN

while the output of the data latch are

internal nodes used for state control. When the

LATCH enable input control pin is a logic 0 (low) the

data latch is transparent and any change to the inputs

will flow directly through the latch to the state control

circuitry and be reflected by a change in the switches

status.

Whenever the LATCH enable control pin is at logic 1,

the data latch is active and data is locked. Subsequent

changes to the input controls IN

, IN

and IN

will not

result in a change to the control logic or affect the

existing switch state.

2.4 T

Pin Description

The T

pin is a bi-directional I/O structure used as an

output to indicate a thermal shutdown event is in effect

and as an input to condition the device into the All-Off

state.

As an output, this pin indicates the status of the

thermal shutdown circuitry. During normal operation

the output will be pulled up to a logic high by an

external resistor tied to the local logic supply voltage.

Under a line fault situation that creates excess thermal

loading, the CPC7508 will enter thermal shutdown

and a logic low will be output.

As an input, the T

pin is utilized to place the

CPC7508 into the “All-Off” state by simply pulling the

input to a logic low. Clare recommends the use of an

open-collector or an open-drain type output from the

control logic to manage the All-Off state using the T

pin.

Forcing T

to a logic 1 or tying this pin to V

will not

prevent normal operation of the thermal shutdown

circuitry inside the CPC7508. It will however prevent

the user from detecting a thermal shutdown condition

and is therefore not recommended.

CPC7508

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Neither the T

input control nor the T

output

functions are affected by the latch function. Since

internal thermal shutdown control and external “All-off”

control is not affected by the state of the LATCH

enable input, T

will override state control.

2.5 Power Supplies

Only a +12 V supply and ground are connected to the

CPC7508. Switch state control is powered exclusively

by the +12 V supply while internal level shifters

provide the necessary translation from the low voltage

inputs to the switch driver circuitry.

2.6 Protection

The CPC7508 uses a combination of current limiting

and a thermal shutdown mechanism to protect the

SLIC device and itself from damage during transient

line faults such as lightning.

For power induction or power-cross fault conditions

the DC current limit function restricts the maximum

current through the switches. Excess power

dissipation during current limiting events will trigger

the thermal shutdown circuit to shut down all of the

switches.

2.6.1 Current Limiting function

If a lightning strike transient occurs when any of the

devices switches are operating, the current will be

restricted by the dynamic current limit response of the

active switches. For instance, during the talk state,

when a 1000V 10x1000 μs lightning pulse

(GR-1089-CORE) is applied to the line though a

properly clamped external protector, the current seen

at T

LINE

and R

LINE

will be a pulse with a typical

magnitude of 2.5 A and a duration less than 0.5 μs.

If a power-cross fault occurs with the device in the talk

state, the current is passed though the break switches

SW1 and SW2 but is limited by the DC current limit

response of the two break switches. The DC current

limit specified over temperature is between 80 mA and

425 mA and the circuitry has a negative temperature

coefficient. As a result, if the device is subjected to

extended heating due to a power cross fault condition,

the measured current at T

LINE

and R

LINE

will decrease

as the device temperature increases. If the device

temperature rises sufficiently, the temperature

shutdown mechanism will activate and the device will

enter the all-off state.

2.6.2 Thermal Shutdown

The thermal shutdown mechanism activates when the

device die temperature reaches a minimum of 110° C,

placing the device in the all-off state regardless of

logic input. During thermal shutdown events the T

pin will output a logic low with a nominal 0 V level. A

logic high is output from the T

pin during normal

operation with a typical output level equal to V

If presented with a short duration transient such as a

lightning event, the thermal shutdown feature will

typically not activate. But in an extended power-cross

event, the device temperature will rise and the thermal

shutdown mechanism will activate forcing the switches

to the all-off state. At this point the current measured

into T

LINE

or R

LINE

will drop to zero. Once the device

enters thermal shutdown it will remain in the all-off

state until the temperature of the device drops below

the de-activation level of the thermal shutdown circuit.

This permits the device to autonomously return to

normal operation. If the transient has not passed,

current will again flow up to the value allowed by the

dynamic DC current limiting of the switches and

heating will resume, reactivating the thermal shutdown

mechanism. This cycle of entering and exiting the

thermal shutdown mode will continue as long as the

fault condition persists. If the magnitude of the fault

condition is great enough, the external secondary

protector will activate shunting the fault current to

ground.

2.7 External Protection Elements

The CPC7508 requires only the over voltage

secondary protector normally used to protect the

ringing SLIC placed on the line side of the LCAS. The

secondary protector must limit voltage transients to

levels that do not exceed the breakdown voltage or

input-output isolation barrier of the CPC7508. Use of a

foldback or crowbar type protector is recommended to

minimize stresses on the LCAS.

Consult Clare’s application note, AN-100, “Designing

Surge and Power Fault Protection Circuits for Solid

State Subscriber Line Interfaces” for equations related

to the specifications of external secondary protectors,

fused resistors and PTCs.

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CPC7508BTR

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CPC7508BTR

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