NB3H83905C
http://onsemi.com
7
Table 7. AC CHARACTERISTICS
Symbol
Characteristic Min Typ Max Unit
V
DD
= V
DDO
= 3.135 V to 3.465 V (3.3 V $ 5%); GND = 0 V, T
A
= 405C to +855C (Note 5)
F
max
Input Frequency Crystal 3 40
MHz
Input Frequency Clock (XTAL_IN/CLK) DC 100
t
EN
/ t
DIS
Delay for Output Enable / Disable Time ENABLEx to BCLKn 4 Cycles
tSKEW
DC
Duty Cycle Skew (See Figure 4) 48 52 %
tSKEW
OO
Output to Output Skew Within A Device (same conditions) 0 50 80 ps
FNOISE
PhaseNoise Performance f
out
= 25 MHz
100 Hz off Carrier
1 kHz off Carrier
10 kHz off Carrier
100 kHz off Carrier
123
142
153
164
dBc/Hz
tJIT(F)
RMS Phase Jitter
25 MHz carrier, Integration Range 12 kHz to 20 MHz
25 MHz carrier, Integration Range 100 Hz to 1 MHz
0.08
0.08
ps
tr/tf Output rise and fall times (20%; 80%) 200 800 ps
V
DD
= V
DDO
= 2.375 V to 2.625 V (2.5 V $ 5%); GND = 0 V, T
A
= 405C to +855C (Note 5)
F
max
Input Frequency Crystal 3 40
MHz
Input Frequency Clock (XTAL1) DC 100
t
EN
/ t
DIS
Delay for Output Enable / Disable Time ENABLEx to BCLKn 4 Cycles
tSKEW
DC
Duty Cycle Skew (See Figure 4) 47 53 %
tSKEW
OO
Output to Output Skew Within A Device (same conditions) 0 50 80 ps
FNOISE
PhaseNoise Performance f
out
= 25 MHz
100 Hz off Carrier
1 kHz off Carrier
10 kHz off Carrier
100 kHz off Carrier
118
137
151
165
dBc/Hz
tJIT(F)
RMS Phase Jitter
25 MHz carrier, Integration Range 12 kHz to 20 MHz
25 MHz carrier, Integration Range 100 Hz to 1 MHz
0.13
0.13
ps
tr/tf Output rise and fall times (20%; 80%) 200 800 ps
V
DD
= V
DDO
= 1.6 V to 2.0 V (1.8 V $ 0.2 V); GND = 0 V, T
A
= 405C to +855C (Note 5)
F
max
Input Frequency Crystal 3 40
MHz
Input Frequency Clock (XTAL1) DC 100
t
EN
/ t
DIS
Delay for Output Enable / Disable Time ENABLEx to BCLKn 4 Cycles
tSKEW
DC
Duty Cycle Skew (See Figure 4) 47 53 %
tSKEW
OO
Output to Output Skew Within A Device (same conditions) 0 50 80 ps
FNOISE
PhaseNoise Performance f
out
= 25 MHz
100 Hz off Carrier
1 kHz off Carrier
10 kHz off Carrier
100 kHz off Carrier
129
145
147
157
dBc/Hz
tJIT(F)
RMS Phase Jitter
25 MHz carrier, Integration Range 12 kHz to 20 MHz
25 MHz carrier, Integration Range 100 Hz to 1 MHz
0.27
0.27
ps
tr/tf Output rise and fall times (20%; 80%) 200 900 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
5. Crystal inputs v F
max
. Outputs loaded with 50 W to V
DDO
/2. CLOCK (LVCMOS levels at XTAL1 input) 50% duty cycle.
See Figures 4 and 7. See APPLICATION INFORMATION; Crystal Input Interface for CL loading.
NB3H83905C
http://onsemi.com
8
Table 7. AC CHARACTERISTICS (continued)
Symbol UnitMaxTypMinCharacteristic
V
DD
= 3.135 V to 3.465 V (3.3 V $5%); V
DDO
= 2.375 V to 2.625 V (2.5 V $5%); GND = 0 V, T
A
= 405C to +855C (Note 5)
F
max
Input Frequency Crystal 3 40
MHz
Input Frequency Clock (XTAL_IN/CLK) DC 100
t
EN
/ t
DIS
Delay for Output Enable / Disable Time ENABLEx to BCLKn 4 Cycles
tSKEW
DC
Duty Cycle Skew (See Figure 4) 48 52 %
tSKEW
OO
Output to Output Skew Within A Device (same conditions) 0 50 80 ps
FNOISE
PhaseNoise Performance f
out
= 25 MHz
100 Hz off Carrier
1 kHz off Carrier
10 kHz off Carrier
100 kHz off Carrier
129
145
147
157
dBc/Hz
tJIT(F)
RMS Phase Jitter
25 MHz carrier, Integration Range 12 kHz to 20 MHz
25 MHz carrier, Integration Range 100 Hz to 1 MHz
0.14
0.14
ps
tr/tf Output rise and fall times (20%; 80%) 200 800 ps
V
DD
= 3.135 V to 3.465 V (3.3 V $5%); V
DDO
= 1.6 V to 2.0 V (1.8 V $0.2 V); GND = 0 V, T
A
= 405C to +855C (Note 5)
F
max
Input Frequency Crystal 3 40
MHz
Input Frequency Clock (XTAL1) DC 100
t
EN
/ t
DIS
Delay for Output Enable / Disable Time ENABLEx to BCLKn 4 Cycles
tSKEW
DC
Duty Cycle Skew (See Figure 4) 48 52 %
tSKEW
OO
Output to Output Skew Within A Device (same conditions) 0 50 80 ps
FNOISE
PhaseNoise Performance f
out
= 25 MHz
100 Hz off Carrier
1 kHz off Carrier
10 kHz off Carrier
100 kHz off Carrier
129
145
147
157
dBc/Hz
tJIT(F)
RMS Phase Jitter
25 MHz carrier, Integration Range 12 kHz to 20 MHz
25 MHz carrier, Integration Range 100 Hz to 1 MHz
0.18
0.18
ps
tr/tf Output rise and fall times (20%; 80%) 200 900 ps
V
DD
= 2.375 V to 2.625 V (2.5 V $5%); V
DDO
= 1.6 V to 2.0 V (1.8 V $0.2 V); GND = 0 V, T
A
= 405C to +855C (Note 5)
F
max
Input Frequency Crystal 3 40
MHz
Input Frequency Clock (XTAL1) DC 100
t
EN
/ t
DIS
Delay for Output Enable / Disable Time ENABLEx to BCLKn 4 Cycles
tSKEW
DC
Duty Cycle Skew (See Figure 4) 47 53 %
tSKEW
OO
Output to Output Skew Within A Device (same conditions) 0 50 80 ps
FNOISE
PhaseNoise Performance f
out
= 25 MHz/
100 Hz off Carrier
1 kHz off Carrier
10 kHz off Carrier
100 kHz off Carrier
129
145
147
157
dBc/Hz
tJIT(F)
RMS Phase Jitter
25 MHz carrier, Integration Range 12 kHz to 20 MHz
25 MHz carrier, Integration Range 100 Hz to 1 MHz
0.19
0.19
ps
tr/tf Output rise and fall times (20%; 80%) 200 900 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
5. Crystal inputs v F
max
. Outputs loaded with 50 W to V
DDO
/2. CLOCK (LVCMOS levels at XTAL1 input) 50% duty cycle.
See Figures 4 and 7. See APPLICATION INFORMATION; Crystal Input Interface for CL loading.
NB3H83905C
http://onsemi.com
9
Figure 4. AC Reference Measurement
t
r
t
SKEW
t
f
80%
20%
BCLKx
t
PW
t
P
V
DDO
2
t
SKEWDC
% +
ǒ
t
PW
ńt
P
Ǔ
100%
V
DDO
2
V
DDO
2
V
DDO
2
V
DDO
2
V
DDO
2
V
DDO
2
BCLKx
BCLKy
BCLKx
OO
t
SKEW
OO
Figure 5. Typical Phase Noise Plot of the NB3H83905C Operating at 25 MHz V
DD
= V
DDO
= 3.3 V

NB3H83905CMNG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 1.8V/2.5V/3.3 V BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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