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AD9762ARURL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
DYNAMIC SPECIFICATIONS
Parameter Min Typ Max Units
DYNAMIC PERFORMANCE
Maximum Output Update Rate (f
CLOCK
) 125 MSPS
Output Settling Time (t
ST
) (to 0.1%)
1
35 ns
Output Propagation Delay (t
PD
)1ns
Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%)
1
2.5 ns
Output Fall Time (10% to 90%)
1
2.5 ns
Output Noise (I
OUTFS
= 20 mA) 50 pA/√Hz
Output Noise (I
OUTFS
= 2 mA) 30 pA/√Hz
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
f
CLOCK
= 25 MSPS; f
OUT
= 1.00 MHz
T
A
= +25°C 75 79 dBc
T
MIN
to T
MAX
73 dBc
f
CLOCK
= 50 MSPS; f
OUT
= 1.00 MHz 79 dBc
f
CLOCK
= 50 MSPS; f
OUT
= 2.51 MHz 74 dBc
f
CLOCK
= 50 MSPS; f
OUT
= 5.02 MHz 70 dBc
f
CLOCK
= 50 MSPS; f
OUT
= 20.2 MHz 57 dBc
f
CLOCK
= 100 MSPS; f
OUT
= 2.51 MHz 73 dBc
f
CLOCK
= 100 MSPS; f
OUT
= 5.04 MHz 67 dBc
f
CLOCK
= 100 MSPS; f
OUT
= 20.2 MHz 57 dBc
f
CLOCK
= 100 MSPS; f
OUT
= 40.4 MHz 53 dBc
Spurious-Free Dynamic Range within a Window
f
CLOCK
= 25 MSPS; f
OUT
=1.00 MHz; 2 MHz Span
T
A
= +25°C 78 86 dBc
T
MIN
to T
MAX
76 dBc
f
CLOCK
= 50 MSPS; f
OUT
= 5.02 MHz; 2 MHz Span 84 dBc
f
CLOCK
= 100 MSPS; f
OUT
= 5.04 MHz; 4 MHz Span 84 dBc
Total Harmonic Distortion
f
CLOCK
= 25 MSPS; f
OUT
= 1.00 MHz
T
A
= +25°C –78 –74 dBc
T
MIN
to T
MAX
–72 dBc
f
CLOCK
= 50 MHz; f
OUT
= 2.00 MHz –75 dBc
f
CLOCK
= 100 MHz; f
OUT
= 2.00 MHz –75 dBc
Multitone Power Ratio (8 Tones at 110 kHz Spacing)
f
CLOCK
= 20 MSPS; f
OUT
= 2.00 MHz to 2.99 MHz 73 dBc
NOTES
1
Measured single ended into 50 Ω load.
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA, Differential Transformer Coupled Output,
50 ⍀ Doubly Terminated, unless otherwise noted)
AD9762
–3–
REV. B
AD9762
–4–
REV. B
DIGITAL SPECIFICATIONS
Parameter Min Typ Max Units
DIGITAL INPUTS
Logic “1” Voltage @ DVDD = +5 V 3.5 5 V
Logic “1” Voltage @ DVDD = +3 V 2.1 3 V
Logic “0” Voltage @ DVDD = +5 V 0 1.3 V
Logic “0” Voltage @ DVDD = +3 V 0 0.9 V
Logic “1” Current –10 +10 µA
Logic “0” Current –10 +10 µA
Input Capacitance 5 pF
Input Setup Time (t
S
) 2.0 ns
Input Hold Time (t
H
) 1.5 ns
Latch Pulsewidth (t
LPW
) 3.5 ns
Specifications subject to change without notice.
0.1%
0.1%
t
S
t
H
t
LPW
t
PD
t
ST
DB0–DB11
CLOCK
IOUTA
OR
IOUTB
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
With
Parameter Respect to Min Max Units
AVDD ACOM –0.3 +6.5 V
DVDD DCOM –0.3 +6.5 V
ACOM DCOM –0.3 +0.3 V
AVDD DVDD –6.5 +6.5 V
CLOCK, SLEEP DCOM –0.3 DVDD + 0.3 V
Digital Inputs DCOM –0.3 DVDD + 0.3 V
IOUTA, IOUTB ACOM –1.0 AVDD + 0.3 V
COMP1, COMP2 ACOM –0.3 AVDD + 0.3 V
REFIO, FSADJ ACOM –0.3 AVDD + 0.3 V
REFLO ACOM –0.3 +0.3 V
Junction Temperature +150 °C
Storage Temperature –65 +150 °C
Lead Temperature
(10 sec) +300 °C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.
ORDERING GUIDE
Temperature Package Package
Model Range Description Option*
AD9762AR –40°C to +85°C 28-Lead 300 mil SOIC R-28
AD9762ARU –40°C to +85°C 28-Lead TSSOP RU-28
AD9762-EB Evaluation Board
*R = SOIC, RU = TSSOP.
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 300 mil SOIC
θ
JA
= 71.4°C/W
θ
JC
= 23°C/W
28-Lead TSSOP
θ
JA
= 97.9°C/W
θ
JC
= 14.0°C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9762 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
(T
MIN
to T
MAX
, AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA unless otherwise noted)
WARNING!
ESD SENSITIVE DEVICE
AD9762
–5–
REV. B
PIN CONFIGURATION
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
AD9762
NC = NO CONNECT
(MSB) DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NC
NC
CLOCK
DVDD
DCOM
NC
AVDD
COMP2
IOUTA
IOUTB
ACOM
COMP1
FS ADJ
REFIO
REFLO
SLEEP
PIN DESCRIPTIONS
Pin No. Name Description
1 DB11 Most Significant Data Bit (MSB).
2–11 DB10–DB1 Data Bits 1–10.
12 DB0 Least Significant Data Bit (LSB).
13, 14, 25 NC No Internal Connection.
15 SLEEP Power-down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated if
not used.
16 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
17 REFIO Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to
AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).
Requires 0.1 µF capacitor to ACOM when internal reference activated.
18 FS ADJ Full-Scale Current Output Adjust.
19 COMP1 Bandwidth/Noise Reduction Node. Add 0.1 µF to AVDD for optimum performance.
20 ACOM Analog Common.
21 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s.
22 IOUTA DAC Current Output. Full-scale current when all data bits are 1s.
23 COMP2 Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor.
24 AVDD Analog Supply Voltage (+2.7 V to +5.5 V).
26 DCOM Digital Common.
27 DVDD Digital Supply Voltage (+2.7 V to +5.5 V).
28 CLOCK Clock Input. Data latched on positive edge of clock.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

AD9762ARURL7

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Digital to Analog Converters - DAC 12-Bit 100 MSPS
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