11 of 30 July 17, 2012
Device Diagram
Device Interface
The TSE2002GB2A1 behaves as a slave device in the I
2
C protocol, with all memory operations synchronized by the serial clock. Read and Write
operations are initiated by a START condition, generated by the bus master. The START condition is followed by a Device Select Code and R/W# bit
(as described in the I
2
C Operating Mode table), terminated by an acknowledge bit. The TSE2002GB2A1 does not initiate clock stretching which is an
optional I
2
C bus feature.
In accordance with the I
2
C bus definition, the device uses three (3) built-in, 4-bit Device Type Identifier Codes (DTIC) and the state of SA0, SA1,
and SA2 to generate an I
2
C Slave Address. The SPD memory may be accessed using a DTIC of (1010), and to perform the PSWP,CSWP, or PSWP
operations a DTIC of (0110) is required. The TS registers are accessed using a DTIC of (0011).
When writing data to the memory, the SPD inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When
data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Bus
Master generated STOP condition after an Ack for WRITE, and after a NoAck for READ.
The TS section of the device uses a pointer register to access all registers in the device.
Additionally, all data transfers to and from this section of the device are performed as block read/ write operations. The data is transmitted/received
as 2 bytes, Most Significant Byte (MSB) first, and terminated with a NoAck and STOP after the Least Significant byte (LSB). Data and address infor-
mation is transmitted and received starting with the Most Significant Bit.first
