MPC9600 REVISION 6 MARCH 15, 2016 9 ©2013 Integrated Device Technology, Inc.
MPC9600 Data Sheet LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER
Power Supply Filtering
The MPC9600 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if this
noise is seen on the power supply pins. Random noise on the
V
CCA
(PLL) power supply impacts the device characteristics, for
instance I/O jitter. The MPC9600 provides separate power
supplies for the output buffers (V
CC
) and the phase-locked loop
(V
CCA
) of the device.The purpose of this design technique is to
isolate the high switching noise digital outputs from the relatively
sensitive internal analog phase-locked loop. In a digital system
environment where it is more difficult to minimize noise on the
power supplies a second level of isolation may be required. The
simple but effective form of isolation is a power supply filter on the
V
CCA
pin for the MPC9600. Figure 5 illustrates a typical power
supply filter scheme. The MPC9600 frequency and phase stability
is most susceptible to noise with spectral content in the 100 kHz
to 20 MHz range. Therefore the filter should be designed to target
this range. The key parameter that needs to be met in the final
filter design is the DC voltage drop across the series filter resistor
R
F
. From the data sheet the I
CCA
current (the current sourced
through the V
CCA
pin) is typically 3 mA (5 mA maximum),
assuming that a minimum of 2.325 V (V
CC
=3.3V or V
CC
=2.5 V)
must be maintained on the V
CCA
pin. The resistor R
F
shown in
Figure 5, must have a resistance of 9–10 (V
CC
= 2.5 V) to meet
the voltage drop criteria.
The minimum values for R
F
and the filter capacitor C
F
are
defined by the required filter characteristics: the RC filter should
provide an attenuation greater than 40 dB for noise whose
spectral content is above 100 kHz. In the example RC filter shown
in Figure 5, the filter cut-off frequency is around 3-5 kHz and the
noise attenuation at 100 kHz is better than 42 dB.
Figure 5. V
CCA
Power Supply Filter
As the noise frequency crosses the series resonant point of an
individual capacitor its overall impedance begins to look inductive
and thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance path
to ground exists for frequencies well above the bandwidth of the
PLL. Although the MPC9600 has several design features to
minimize the susceptibility to power supply noise (isolated power
and grounds and fully differential PLL) there still may be
applications in which overall performance is being degraded due
to system power supply noise. The power supply filter schemes
discussed in this section should be adequate to eliminate power
supply noise related problems in most designs.
Using the MPC9600 in Zero-Delay Applications
Nested clock trees are typical applications for the MPC9600.
For these applications the MPC9600 offers a differential LVPECL
clock input pair as a PLL reference. This allows for the use of
differential LVPECL primary clock distribution devices such as the
Freescale Semiconductor MC100ES6111 or MC100ES6226,
taking advantage of its superior low-skew performance. Clock
trees using LVPECL for clock distribution and the MPC9600 as
LVCMOS PLL fanout buffer with zero insertion delay will show
significantly lower clock skew than clock distributions developed
from CMOS fanout buffers.
The external feedback option of the MPC9600 PLL allows for
its use as a zero delay buffer. The PLL aligns the feedback clock
output edge with the clock input reference edge and virtually
eliminates the propagation delay through the device.
The remaining insertion delay (skew error) of the MPC9600 in
zero-delay applications is measured between the reference clock
input and any output. This effective delay consists of the static
phase offset (SPO or t
()
), I/O jitter (t
JIT()
, phase or long-term
jitter), feedback path delay and the output-to-output skew (t
SK(O)
)
relative to the feedback output.
Calculation of Part-to-Part Skew
The MPC9600 zero delay buffer supports applications where
critical clock signal timing can be maintained across several
devices. If the reference clock inputs (CCLK or PCLK) of two or
more MPC9600 are connected together, the maximum overall
timing uncertainty from the common CCLK input to any output is:
t
SK(PP)
= t
()
+ t
SK(O)
+ t
PD, LINE(FB)
+ t
JIT()
CF
This maximum timing uncertainty consist of 4 components:
static phase offset, output skew, feedback board trace delay and
I/O (phase) jitter:
Figure 6. MPC9600 Maximum Device-to-Device Skew
V
CCA
V
CC
MPC9600
10 nFC
F
R
F
V
CC
33...100 nF
R
F
= 9–10 for V
CC
= 2.5 V or V
CC
= 3.3 V
C
F
= 22 F for V
CC
= 2.5 V or V
CC
= 3.3 V
t
PD,LINE(FB)
t
JIT()
+t
SK(O)
—t
()
+t
()
t
JIT()
+t
SK(O)
t
SK(PP)
Max. skew
TCLK
Common
QFB
Device 1
Any Q
Device 1
QFB
Device2
Any Q
Device 2
