9
LTC2847
sn2847 2847fs
Mode Name M2 M1 M0 DCE/ D1,2 D3 D1 D2 D3 R1 R2 R3 R1 R2,R3 V
DD
V
EE
DTE (Note 2) (Note 2) (Note 2) (Note 3) (Note 3) (Note 4) (Note 5)
ABABABABABAB
Not Used
(Default V.11) 0 0 0 0 TTL X V.11 V.11 V.11 V.11 Z Z V.11 V.11 V.11 V.11 V.11 V.11 CMOS CMOS 9.3V –6V
RS530A 0 0 1 0 TTL X V.11 V.11 V.11 V.11 Z Z V.11 V.11 V.11 V.11 V.11 V.11 CMOS CMOS 9.3V –6V
RS530 0 1 0 0 TTL X V.11 V.11 V.11 V.11 Z Z V.11 V.11 V.11 V.11 V.11 V.11 CMOS CMOS 9.3V –6V
X.21 0 1 1 0 TTL X V.11 V.11 V.11 V.11 Z Z V.11 V.11 V.11 V.11 V.11 V.11 CMOS CMOS 9.3V –6V
V.35 1 0 0 0 TTL X V.35 V.35 V.35 V.35 Z Z V.35 V.35 V.35 V.35 V.35 V.35 CMOS CMOS 8V –6.5V
RS449/V.36 1 0 1 0 TTL X V.11 V.11 V.11 V.11 Z Z V.11 V.11 V.11 V.11 V.11 V.11 CMOS CMOS 9.3V –6V
V.28/RS232 1 1 0 0 TTL X V.28 Z V.28 Z Z Z V.28 30k V.28 30k V.28 30k CMOS CMOS 8.7V –8.5V
No Cable 1 1 1 0 X X ZZZZZZ30k30k30k30k30k30kZ Z 4.7V 0.3V
Not Used
(Default V.11) 0 0 0 1 TTL TTL V.11 V.11 V.11 V.11 V.11 V.11 30k 30k V.11 V.11 V.11 V.11 Z CMOS 9.3V –6V
RS530A 0 0 1 1 TTL TTL V.11 V.11 V.11 V.11 V.11 V.11 30k 30k V.11 V.11 V.11 V.11 Z CMOS 9.3V –6V
RS530 0 1 0 1 TTL TTL V.11 V.11 V.11 V.11 V.11 V.11 30k 30k V.11 V.11 V.11 V.11 Z CMOS 9.3V –6V
X.21 0 1 1 1 TTL TTL V.11 V.11 V.11 V.11 V.11 V.11 30k 30k V.11 V.11 V.11 V.11 Z CMOS 9.3V –6V
V.35 1 0 0 1 TTL TTL V.35 V.35 V.35 V.35 V.35 V.35 30k 30k V.35 V.35 V.35 V.35 Z CMOS 8V –6.5V
RS449/V.36 1 0 1 1 TTL TTL V.11 V.11 V.11 V.11 V.11 V.11 30k 30k V.11 V.11 V.11 V.11 Z CMOS 9.3V –6V
V.28/RS232 1 1 0 1 TTL TTL V.28 Z V.28 Z V.28 Z 30k 30k V.28 30k V.28 30k Z CMOS 8.7V –8.5V
No Cable 1 1 1 1 X X ZZZZZZ30k30k30k30k30k30kZ Z 4.7V 0.3V
SWITCHI G TI E WAVEFOR S
UWW
Figure 14. V.11, V.35 Receiver Propagation Delays
Figure 13. V.11, V.35 Driver Propagation Delays
ODE SELECTIO
W
U
Table 1
3V
1.5V 1.5V
50%
10%
90%
t
PLH
t
r
0V
V
O
V
O
–V
O
D
B – A
A
B
t
PHL
t
SKEW
t
SKEW
2847 F13
1/2 V
O
f = 1MHz : t
r
≤ 10ns : t
f
≤ 10ns
50%
10%
90%
t
f
V
OD2
–V
OD2
0V
1.65V
0V
1.65V
t
PLH
V
OH
V
OL
B – A
R
t
PHL
2847 F14
f = 1MHz : t
r
≤ 10ns : t
f
≤ 10ns
INPUT
OUTPUT
Note 1: Driver inputs are TTL level compatible.
Note 2: Unused receiver inputs are terminated with 30k to ground. In addition, R2 and R3 are always
terminated by a 103Ω differential impedence (see Block Diagram on page 7).
Note 3: Receiver Outputs are CMOS level compatible and have a weak pull up to V
IN
when Z.
Note 4: V
DD
values shown are typical values for V
CC
= 5V, V
IN
= 3.3V and T
A
= 25°C with LTC2847
under full load for each mode.
Note 5: V
EE
values shown are typical values for V
CC
= 5V, V
IN
= 3.3V and T
A
= 25°C with LTC2847
under full load for each mode.
(Note 1)
(Note 1)
