MAX13030E–MAX13035E
6-Channel High-Speed Logic-Level Translators
8 _______________________________________________________________________________________
Pin Description
PIN
MAX13030E–MAX13034E MAX13035E
UCSP TQFN UCSP TQFN
NAME FUNCTION
A1 4 A1 4 I/O V
L
3 Input/Output 3. Referenced to V
L
.
A2 6 A2 6 I/O V
CC
3 Input/Output 3. Referenced to V
CC
.
A3 7 A3 7 I/O V
CC
4 Input/Output 4. Referenced to V
CC
.
A4 9 A4 9 I/O V
L
4 Input/Output 4. Referenced to V
L
.
B1 3 B1 3 I/O V
L
2 Input/Output 2. Referenced to V
L
.
B2 5 B2 5 I/O V
CC
2 Input/Output 2. Referenced to V
CC
.
B3 8 B3 8 I/O V
CC
5 Input/Output 5. Referenced to V
CC
.
B4 10 B4 10 I/O V
L
5 Input/Output 5. Referenced to V
L
.
C1 2 C1 2 V
L
Logic-Supply Voltage, +1.62V to +3.2V. Bypass V
L
to GND with
a 0.1µF capacitor placed as close as possible to the device.
C2 16 C2 16 V
CC
Power-Supply Voltage, +2.2V to +3.6V. Bypass V
CC
to GND with
a 0.1µF ceramic capacitor. For full ESD protection, connect a
1µF ceramic capacitor from V
CC
to GND as close as possible to
the V
CC
input.
C3 13 C3 13 GND Ground
C4 11 — — EN
Enable Input. Drive EN to GND for shutdown mode, or drive EN to
V
L
or V
CC
for normal operation.
D1 1 D1 1 I/O V
L
1 Input/Output 1. Referenced to V
L
.
D2 15 D2 15 I/O V
CC
1 Input/Output 1. Referenced to V
CC
.
D3 14 — — I/O V
CC
6 Input/Output 6. Referenced to V
CC
.
D4 12 — — I/O V
L
6 Input/Output 6. Referenced to V
L
.
— — C4 11 CLK_RET
Clock Return Output. CLK_RET is the returned signal of a clock
applied to CLK_V
L
. CLK_RET is referenced to V
L
.
— — D3 14 CLK_V
CC
Translator Channel for a Clock Applied to V
CC
— — D4 12 CLK_V
L
Translator Channel for a Clock Applied to V
L
— EP — EP EP Exposed Paddle. Connect exposed paddle to GND.
