DC1620A-B Datasheet DC1620A-H, DC1620A-O, DC1620A-M | P4-P6

dc1620afb

DEMO MANUAL DC1620A

QUICK START PROCEDURE

Using bandpass filters on the clock and the analog input

will improve the noise performance by reducing the

wideband noise power of the signals. In the case of the

DC1620A a bandpass filter used for the clock should be

used prior to the DC1075. Data sheet FFT plots are taken

with 10-pole LC filters made by TTE (Los Angeles, CA) to

suppress signal generator harmonics, non-harmonically

related spurs and broadband noise. Low phase noise Agilent

8644B generators are used with TTE bandpass filters for

both the clock input and the analog input.

Apply the analog input signal of interest to the SMA con-

nectors on the DC1620A demonstration circuit board

marked J5 AIN+. These inputs are capacitive coupled to

Balun transformers ETC1-1-13 (lead free part number:

MABA007159-000000).

An internally generated conversion clock output is available

on J1 which could be collected via a logic analyzer, or other

data collection system if populated with a SAMTEC MEC8-

150 type connector or collected by the DC890 QuikEval™-II

data acquisition board using PScope™ software.

Software

The DC890 is controlled by the PScope system software

provided or downloaded from the Linear Technology

website at http://www.linear.com/software/. If a DC890

was provided, follow the DC890 Quick Start Guide and

the instructions below.

To start the data collection software if “PScope.exe” is

installed (by default) in \Program Files\LTC\PScope\, double

click the PScope icon or bring up the run window under

the start menu and browse to the PScope directory and

select PScope.

If the DC1620A demonstration circuit is properly connected

to the DC890, PScope should automatically detect the

DC1620A, and configure itself accordingly. If necessary

the procedure below explains how to manually configure

PScope.

Under the Configure menu, go to ADC Configuration. Check

the Config Manually box and use the following configura-

tion options, see Figure 2:

Manual configuration settings:

Bits: 16

Alignment: 16

FPGA Ld: DDR LVDS

Channs: 2

Bipolar: Unchecked

Positive-Edge Clk: Checked

If everything is hooked up properly, powered, and a suitable

convert clock is present, clicking the Collect button will

result in time and frequency plots displayed in the PScope

window. Additional information and help for PScope is

available in the DC890 Quick Start Guide and in the online

help available within the PScope program itself.

Serial Programming

PScope has the ability to program the DC1620A board

serially through the DC890. There are several options

available in the LTC2185 family that are only available

through serially programming. PScope allows all of these

features to be tested.

These options are available by first clicking on the Set

Demo Bd Options icon on the PScope toolbar (Figure 3).

Figure 2: ADC Configuration

dc1620afb

DEMO MANUAL DC1620A

QUICK START PROCEDURE

This will bring up the menu shown in Figure 4.

• Nap – ADC core powers down while references stay

active

• Shutdown – The entire ADC is powered down

Clock Inversion: Selects the polarity of the CLKOUT signal.

• Normal (Default) – Normal CLKOUT polarity

• Inverted – CLKOUT polarity is inverted

Clock Delay: Selects the phase delay of the CLKOUT signal.

• None (Default) – No CLKOUT delay

• 45° – CLKOUT delayed by 45°

• 90° – CLKOUT delayed by 90°

• 135° – CLKOUT delayed by 135°

Clock Duty Cycle: Enable or disables Duty Cycle Stabilizer.

• Stabilizer off (Default) – Duty cycle stabilizer disabled

• Stabilizer on – Duty cycle stabilizer enabled

Output Current: Selects the LVDS output drive current.

• 1.75mA (Default) - LVDS output driver current

• 2.1mA – LVDS output driver current

• 2.5mA – LVDS output driver current

• 3.0mA – LVDS output driver current

• 3.5mA – LVDS output driver current

• 4.0mA – LVDS output driver current

• 4.5mA – LVDS output driver current

Internal Termination: Enables LVDS internal termination.

• Off (Default) – Disables internal termination

• On – Enables internal termination

Outputs: Enables digital outputs.

• Enabled (Default) – Enables digital outputs

• Disabled – Disables digital outputs

Output Mode: Selects digital output mode.

• Full Rate – Full rate CMOS output mode (This mode is

not supported by the DC1620A)

Figure 3: PScope Toolbar

Figure 4: Demobd Configuration Options

This menu allows any of the options available for the

LTC2185/LTC2145 family to be programmed serially. The

LTC2185/LTC2145 family has the following options:

Power Control: Selects between normal operation, nap

and sleep modes.

• Normal (Default) – Entire ADC is powered, and active

• Ch1 Normal Ch2 Nap – Channel 1 remains active while

channel 2 is put into nap mode

dc1620afb

DEMO MANUAL DC1620A

• Double LVDS (Default) – double data rate LVDS output

mode

• Double CMOS – double data rate CMOS output mode

(This mode is not supported by the DC1620A)

Test Pattern: Selects Digital output test patterns.

• Off (Default) – ADC data presented at output

• All out =1 – All digital outputs are 1

• All out = 0 – All digital outputs are 0

• Checkerboard - OF, and D13-D0 Alternate between 101

0101 1010 0101 and 010 1010 0101 1010 on alternat-

ing samples

• Alternating – Digital outputs alternate between all 1’s

and all 0’s on alternating samples

QUICK START PROCEDURE

Alternate Bit: Alternate bit polarity (ABP) Mode.

• Off (Default) – Disables alternate bit polarity

• On – Enables alternate bit polarity (before enabling ABP,

be sure the part is in offset binary mode)

Randomizer: Enables data output randomizer.

• Off (Default) – Disables data output randomizer

• On – Enables data output randomizer

Two’s complement: Enables two’s complement mode.

• Off (Default) – Selects offset binary mode

• On – Selects two’s complement mode

Once the desired settings are selected hit OK and PScope

will automatically update the register of the device on the

DC1620A demo board.

PARTS LIST

ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER

11CN1 CAP, ARRAY, 0508 2.2μF 20% 10V X5R AVX W0508L8ZD225MAT1A

2 7 R47, R48, R53, R54, R78, R79 RES, 0402 0Ω JUMPER NIC NRC04Z0TRF

3 11 C1, C2, C3, C6, C7, C13, C57-C61, C65 CAP, 0402 0.01μF 10% 16V X7R AVX 0402YC103KAT

4 4 C9, C10, C63, C64 CAP, 0402 8.2pF 5% 50V COG AVX 04025A8R2JAT2A

5 0 C11, C16 CAP, 0402 OPTION OPTION

6 9 C12, C15, C18-C21, C37, C66, C67 CAP, 0402 0.1μF 10% 10V X5R TDK C1005X5R1A104K

7 4 C14, C22, C72, C73 CAP, 0603 1μF 10% 16V X7R TDK C1608X7R1C105K

8 2 C17, C23 CAP, 0402 2.2μF 20% 6.3V X5R TAIYO YUDEN JMK105BJ225MV-T

9 1 C24 CAP, 0603 4.7μF 20% 6.3V X5R TDK C1608X5R0J475MT

10 13 C26-C32, C34-C36, C56, C75, C76 CAP, 0603 0.1μF 10% 50V X7R TDK C1608X7R1H104K

11 0 C33, C70, C71 CAP, 0603 OPTION OPTION

12 2 C51, C62 CAP, 0402 4.7pF ±0.25pF 50V NPO AVX 04025A4R7CAT2A

13 2 C54, C55 CAP, 0805 10μF 10% 16V X5R MURATA GRM21BR61C106KE15L

14 3 C68, C69, C74 CAP, 0402 22pF 5% 16V NPO AVX 0402YA220JAT2A

15 5 JP2, JP3, JP4, JP5, JP6 HEADER, 3-PIN, 2mm SAMTEC TMM-103-02-L-S

16 4 J1, J2, J3, J4 CONN, BNC, SMA 50-OHM EDGE-LANCH E.F. JOHNSON, 142-0701-851

17 2 L1, L6 IND, 0603 56μH 5% MURATA LQP18MN56NG02D

18 3 L2, L3, L4 FERRITE BEAD, 1206 MURATA BLM31PG330SN1L

19 0 L5 IND, 0603 BEAD TBD

P1-P3 P4-P6 P7-P9 P10-P10

DC1620A-B

Mfr. #:

Buy DC1620A-B

Manufacturer:

Analog Devices Inc.

Description:

Data Conversion IC Development Tools LTC2184: 16-bit 105Msps Dual ADC, DDR LV

Lifecycle:

New from this manufacturer.

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DC1620A-B

DC1620A-B

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