DC1620A-O Datasheet DC1620A-H, DC1620A-O, DC1620A-M | P1-P3

dc1620afb

DEMO MANUAL DC1620A

DESCRIPTION

LTC2185, LTC2184, LTC2183,

LTC2182, LTC2181, LTC2180, LTC2188, LTC2145-14/-12,

LTC2144-14/-12, LTC2143-14/-12, LTC2142-14/-12, LTC2141-14/-12,

LTC2140-14/-12, LTC2270: 16-/14-/12-Bit,

20Msps to 125Msps Dual ADCs

Demonstration circuit 1620A supports a family of

16-/14-/12-bit, 20Msps to 125Msps ADCs. Each assembly

features one of the following devices: LTC

2185, LTC2184,

LTC2183, LTC2182, LTC2181, LTC2180, LTC2188,

LTC2145-14, LTC2144-14, LTC2143-14, LTC2142-14,

LTC2141-14, LTC2140-14, LTC2145-12, LTC2144-12,

LTC2143-12, LTC2142-12, LTC2141-12, or LTC2140-12,

LTC2270 high speed, high dynamic range ADCs.

Demonstration circuit 1620A supports the LTC2185/

LTC2145 family DDR LVDS output mode.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

QuikEval and PScope are trademarks of Linear Technology Corporation. All other trademarks are

the property of their respective owners.

The versions of the 1620A demo board supporting the

LTC2185 and LTC2145 series of A/D converters are listed

in Table 1. Depending on the required resolution and

sample rate, the DC1620A is supplied with the appropri-

ate ADC. The circuitry on the analog inputs is optimized

for analog input frequencies from 5MHz to 70MHz. Refer

to the data sheet for proper input networks for different

input frequencies.

Design files for this circuit board are available at

http://www.linear.com/demo

Table 1. DC1620 Variants

DC1620 VARIANTS ADC PART NUMBER RESOLUTION MAXIMUM SAMPLE RATE INPUT FREQUENCY

1620A-A LTC2185 16-Bit 125Msps 5MHz to 140MHz

1620A-B LTC2184 16-Bit 105Msps 5MHz to 140MHz

1620A-C LTC2183 16-Bit 80Msps 5MHz to 140MHz

1620A-D LTC2182 16-Bit 65Msps 5MHz to 140MHz

1620A-E LTC2181 16-Bit 40Msps 5MHz to 140MHz

1620A-F LTC2180 16-Bit 25Msps 5MHz to 140MHz

1620A-G LTC2145-14 14-Bit 125Msps 5MHz to 140MHz

1620A-H LTC2144-14 14-Bit 105Msps 5MHz to 140MHz

1620A-I LTC2143-14 14-Bit 80Msps 5MHz to 140MHz

1620A-J LTC2142-14 14-Bit 65Msps 5MHz to 140MHz

1620A-K LTC2141-14 14-Bit 40Msps 5MHz to 140MHz

1620A-L LTC2140-14 14-Bit 25Msps 5MHz to 140MHz

1620A-M LTC2145-12 12-Bit 125Msps 5MHz to 140MHz

1620A-N LTC2144-12 12-Bit 105Msps 5MHz to 140MHz

1620A-O LTC2143-12 12-Bit 80Msps 5MHz to 140MHz

1620A-P LTC2142-12 12-Bit 65Msps 5MHz to 140MHz

1620A-Q LTC2141-12 12-Bit 40Msps 5MHz to 140MHz

1620A-R LTC2140-12 12-Bit 25Msps 5MHz to 140MHz

1620A-S LTC2188 16-Bit 20Msps 5MHz to 140MHz

1620A-T LTC2270 16-Bit 20Msps 5MHz to 140MHz

dc1620afb

DEMO MANUAL DC1620A

QUICK START PROCEDURE

PERFORMANCE SUMMARY

= 25°C)

PARAMETER CONDITION VALUE

Supply Voltage—DC1620A Depending on Sampling Rate and the A/D Converter

Provided, This Supply Must Provide Up to 500mA

Optimized for 4.5V [4.5V  6.0V Min/Max]

Analog Input Range Depending on SENSE Pin Voltage 1V

P-P

to 2V

P-P

Logic Input Voltages Minimum Logic High 1.3V

Maximum Logic Low 0.6V

Logic Output Voltages (Differential) Nominal Logic Levels (100Ω Load, 3.5mA Mode) 350mV/1.25V Common Mode

Minimum Logic Levels (100Ω Load, 3.5mA Mode) 247mV/1.25V Common Mode

Sampling Frequency (Convert Clock Frequency) See Table 1

Convert Clock Level Single-Ended Encode Mode (ENC– Tied to GND) 0V to 3.6V

Differential Encode Mode (ENC– Not Tied to GND) 0.2V to 3.6V

Resolution See Table 1

Input frequency range See Table 1

SFDR See Applicable Data Sheet

SNR See Applicable Data Sheet

Demonstration circuit 1620A is easy to set up to evaluate

the performance of the LTC2185/LTC2145 A/D converter

family. Refer to Figure 1 for proper measurement equip-

ment setup and follow the procedure below:

Setup

If a DC890 USB data acquisition and collection system

was supplied with the DC1620A demonstration circuit,

follow the DC890 Quick Start Guide to install the required

software and for connecting the DC890 to the DC1620A

and to a PC.

DC1620A Demonstration Circuit Board Jumpers

The DC1620A demonstration circuit board should have

the following jumper settings as default positions: (as

per Figure 1)

JP2-PAR/SER: Selects Parallel or Serial programming

mode. (Default: Serial)

JP3-Duty Cycle Stabilizer: Enables/Disable Duty Cycle

Stabilizer. (Default: Enable)

JP4-SHDN: Enables and disables the LTC2185/LTC2145.

(Default: Enable)

JP5-NAP: Enables and disables NAP mode (Default:

disable)

JP6-LVDS/CMOS: Selects between LVDS and CMOS output

signaling. (Default: LVDS)

Applying Power and Signals to the DC1620A

Demonstration Circuit

If a DC890 is used to acquire data from the DC1620A, the

DC890 must first be connected to a powered USB port

or provided an external 6V to 9V before applying +4.5V

to +6.0V across the pins marked V+ and GND on the

DC1620A. DC1620A requires 4.5V for proper operation.

Regulators on the board produce the voltages required for

the ADC. The DC1620A demonstration circuit requires up

to 500mA depending on the sampling rate and the A/D

converter supplied.

The DC890 data collection board is powered by the USB

cable and does require an external power supply when

collecting data from an LVDS demo board. It must be

supplied from an external 6V to 9V on turrets G7(+) and

G1(–) or the adjacent 2.1mm power jack.

dc1620afb

DEMO MANUAL DC1620A

QUICK START PROCEDURE

Figure 1. DC1620 Setup (Zoom for Detail)

Analog Input Network

For optimal distortion and noise performance, the RC

network on the analog inputs may need to be optimized

for different analog input frequencies. For input frequen-

cies above 140MHz, refer to the respective ADC data sheet

for a proper input network. Other input networks may be

more appropriate for input frequencies less that 5MHz or

above 140MHz.

In almost all cases, filters will be required on both analog

the input and encode clock to provide data sheet SNR. In

the case of the DC1620A a bandpass filter used for the clock

should be used prior to the DC1075 clock divider board.

The filters should be located close to the inputs to avoid

reflections from impedance discontinuities at the driven

end of a long transmission line. Most filters do not present

50Ω outside the passband. In some cases, 3dB to 10dB

pads may be required to obtain low distortion.

If your generator cannot deliver full-scale signals without

distortion, you may benefit from a medium power amplifier

based on a Gallium Arsenide gain block prior to the final

filter. This is particularly true at higher frequencies where

IC-based operational amplifiers may be unable to deliver

the combination of low noise figure and high IP3 point

required. A high order filter can be used prior to this final

amplifier, and a relatively lower Q filter used between the

amplifier and the demo circuit.

Encode Clock

Note: Apply an encode clock to the SMA connector on

the DC1620A demonstration circuit board marked J3.

As a default, the DC1620A is populated to have a single-

ended input.

For the best noise performance, the encode input must

be driven with a very low jitter, square wave source. The

amplitude should be large, up to 3V

P-P

or 13dBm. When

using a sinusoidal signal generator a squaring circuit can

be used. Linear Technology also provides demo board

DC1075 that divides a high frequency sine wave by four,

producing a low jitter square wave for best results with

the LTC2185/LTC2145.

–

ANALOG INPUT

CHANNEL 1

PARALLEL/SERIAL

PROGRAMMING MODE

PARALLEL DATA

OUTPUT TO DC890

DUTY CYCLE

STABILIZER

SHDN

LVDS/CMOS

SINGLE-ENDED

ENCODE CLOCK

FROM DC1075

4.5V TO 6V

NAP

ANALOG INPUT

CHANNEL 2

P1-P3 P4-P6 P7-P9 P10-P10

DC1620A-O

Mfr. #:

Buy DC1620A-O

Manufacturer:

Analog Devices Inc.

Description:

Data Conversion IC Development Tools LTC2143-12: 12-bit 80Msps Dual ADC, DDR

Lifecycle:

New from this manufacturer.

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DC1620A-O

DC1620A-O

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