MK1413SLF Datasheet MK1413SLFTR, MK1413SLF | P1-P3

DATASHEET

MPEG AUDIO CLOCK SOURCE MK1413

IDT™ / ICS™

MPEG AUDIO CLOCK SOURCE 1

MK1413 REV G 051310

Description

The MK1413 is the ideal way to generate clocks for MPEG

audio devices in computers. The device uses IDT’s

proprietary mixture of analog and digital Phase-Locked

Loop (PLL) technology to synthesize one of four frequencies

from the 14.31818 MHz reference. In an 8-pin SOIC, the

MK1413 can save component count, board space, and cost

over crystals and oscillators, and increase reliability by

eliminating three expensive mechanical devices from the

board.

IDT offers many other clocks for computers and computer

peripherals. Consult IDT when you need to remove crystals

and oscillators from your board.

Features

• Packaged in 8-pin SOIC

• Pb (lead) free package

• Input crystal or clock frequency of 14.31818 MHz

• Provides master MPEG clocks for 32 kHz, 44.1 kHz, and

48 kHz sampling rates

• Output clock frequencies of 8.192 MHz, 11.2896 MHz,

12.288 MHz, and 16.9344 MHz

• Low jitter

• 25 mA drive capability at TTL levels (at 5.0 V)

• 3.3 V or 5.0 V (±10%) supply voltage

• Advanced, low-power CMOS process

Block Diagram

CLK

Clock

Synthesis

and Control

Circuitry

14.31818 MHz

crystal or clock

input

VDD

Crystal

Buffer/

Crystal

Oscillator

S1:0

GND

Optional crystal load capacitors

(see page 3 for details)

MK1413

MPEG AUDIO CLOCK SOURCE CLOCK SYNTHESIZER

IDT™ / ICS™

MPEG AUDIO CLOCK SOURCE 2

MK1413 REV G 051310

Pin Assignment

Audio Clock Output Selection Table

Pin Descriptions

VDD

GND S1

CLK

X21

8-pin SOIC

S1 S0 Audio Clock (pin 5) Accuracy (ppm)

0 0 8.192 MHz -2 ppm

0 1 11.2896 MHz -24 ppm

1 0 12.288 MHz -2 ppm

1 1 16.9344 MHz -24 ppm

Number

Name

Type

Pin Description

1 X1 Input Crystal connection. Connect this pin to a 14.31818 MHz crystal or clock.

2 VDD Power Connect to 3.3 V or 5 V.

3 GND Power Connect to ground.

4 NC — No connect.

5 CLK Output Audio clock output as per table above.

6 S1 Input Frequency Select 1 input. Determines CLK output as per table above.

7 S0 Input Frequency Select 0 input. Determines CLK output as per table above.

8 X2 Output Crystal connection to a 14.31818 MHz crystal or leave unconnected for clock input.

MK1413

MPEG AUDIO CLOCK SOURCE CLOCK SYNTHESIZER

IDT™ / ICS™

MPEG AUDIO CLOCK SOURCE 3

MK1413 REV G 051310

Application Information

Series Termination Resistor

Clock output traces should use series termination. For

series terminating a 50Ω trace (a commonly used trace

impedance), place a 33Ω resistor in series with the clock line

and as close to the clock output pin as possible. The

nominal impedance of the clock output is 20Ω.

Crystal Load Capacitors

The device crystal connections should include pads for

capacitors from X1 to ground and from X2 to ground, and a

parallel rsonant 14.31818 MHz crystal is recommended.

These capacitors are used to adjust the stray capacitance of

the board to match the nominally required crystal load

capacitance. To reduce possible noise pickup, use very

short PCB traces (and no vias) been the crystal and device.

The value (in pF) of each crystal load capacitor should equal

-4) x2, where C

is the crystal’s load (correlation)

capacitance in pF. The frequency tolerance of the crystal

should be 50 ppm or better.For a clock input, connect X1

and leave X2 unconnected. Because these capacitors

adjust the stray capacitance of the PCB, check the output

frequency using your final layout to see if the value of C

should be changed.

PCB Layout Recommendations

Observe the following guidelines for optimum device

performance and lowest output phase noise:

1) Each 0.01µF decoupling capacitor should be mounted on

the component side of the board as close to the VDD pin as

possible. No vias should be used between decoupling

capacitor and VDD pin. The PCB trace to VDD pin should

be kept as short as possible, as should the PCB trace to the

ground via. Distance of the ferrite bead and bulk decoupling

from the device is less critical.

2) The external crystal should be mounted next to the device

with short traces. The X1 and X2 traces should not be

routed next to each other with minimum spaces, instead

they should be separated and away from other traces.

3) To minimize EMI, and obtain the best signal integrity, the

33Ω series termination resistor should be placed close to

the clock output.

4) An optimum layout is one with all components on the

same side of the board, minimizing vias through other signal

layers (the ferrite bead and bulk decoupling capacitor can be

mounted on the back). Other signal traces should be routed

away from the MK1413. This includes signal traces just

underneath the device, or on layers adjacent to the ground

plane layer used by the device.

P1-P3 P4-P6 P7-P7

MK1413SLF

Mfr. #:

Buy MK1413SLF

Manufacturer:

Description:

IC AUDIO CLK SOURCE MPEG 8-SOIC

Lifecycle:

New from this manufacturer.

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MK1413SLF

MK1413SLF

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