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2Gb_twindie_H.fm - Rev. B 7/10 EN
6 ©2010 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8 TwinDie DDR2 SDRAM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the devices at these or any other condi-
tions outside those indicated in the device data sheet is not implied. Exposure to abso-
lute maximum rating conditions for extended periods may adversely affect reliability.
Notes: 1. V
DD
, V
DDQ
, and V
DDL
must be within 300mV of each other at all times.
2. V
REF
≤ 0.6 × V
DDQ
; however, V
REF
may be ≥ V
DDQ
provided that V
REF
≤ 300mV.
3. Voltage on any I/O may not exceed voltage on V
DDQ
.
Temperature and Thermal Impedance
It is imperative that the DDR2 SDRAM device’s temperature specifications, shown in
Table 5 on page 7, be maintained to ensure the junction temperature is in the proper
operating range to meet data sheet specifications. An important step in maintaining the
proper junction temperature is using the device’s thermal impedances correctly.
Thermal impedances listed in Table 5 on page 7 apply to the current die revision and its
packages.
Incorrectly using thermal impedances can produce significant errors. Read Micron tech-
nical note TN-00-08: “Thermal Applications” prior to using the thermal impedances in
Table 6 on page 7. For designs that are expected to last several years and require the flex-
ibility to use several DRAM die shrinks, consider using final target theta values (rather
than existing values) to account for increased thermal impedances from the reduction in
die size.
The DDR2 SDRAM device’s safe junction temperature range can be maintained when
the T
C
specifications are not exceeded. In applications where the device’s ambient
temperature is too high, use of forced air and/or heat sinks may be required to satisfy the
case temperature specifications.
Table 4: Absolute Maximum Ratings
Symbol Parameter Min Max Units Notes
V
DD
V
DD
supply voltage relative to V
SS
–1.0 +2.3 V 1
V
DDQ
V
DDQ
supply voltage relative to V
SSQ
–0.5 +2.3 V 1, 2
V
DDL
V
DDL
supply voltage relative to V
SSDL
–0.5 +2.3 V 1
V
IN
, V
OUT
Voltage on any ball relative to V
SS
–0.5 +2.3 V 3
I
I
Input leakage current; Any input 0V ≤ V
IN
≤ V
DD
(All other balls
not under test = 0V)
–10 +10 µA
I
OZ
Output leakage current; 0V ≤ V
OUT
≤ V
DDQ
; DQ and ODT are
disabled
–10 +10 µA
I
VREF
V
REF
leakage current; V
REF
= valid V
REF
level
–4 +4 µA
