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2Gb_twindie_H.fm - Rev. B 7/10 EN
3 ©2010 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8 TwinDie DDR2 SDRAM
Ball Assignments and Descriptions
Table 3: 63-Ball FBGA Ball Descriptions – x4, x8
Symbol Type Description
A[13:0] Input
Address inputs: Provide the row address for ACTIVE commands, and the column address and
auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory
array in the respective bank. A10 sampled during a precharge command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA[2:0]) or all
device banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE
command.
BA[2:0] Input
Bank address inputs: BA[2:0] define the bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA[2:0] define which mode register (MR, EMR1, EMR2,
and EMR3) is loaded during the LOAD MODE command.
CK, CK# Input
Clock: CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#.
CKE[1:0] Input
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) the internal
circuitry and clocks on the DDR2 SDRAM.
DM Input
Input data mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH, along with the input data, during a write access. DM is sampled on both edges
of DQS. Although the DM balls are input-only, DM loading is designed to match that of the DQ
and DQS balls.
ODT[1:0] Input
On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR2 SDRAM. When enabled in normal operation, ODT
is applied only to the following balls: DQ, DQS, DQS#, and DM. The ODT input will be ignored if
disabled via the LOAD MODE command.
RAS#, CAS#,
WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being
entered.
CS#[1:0] Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command
decoder.
DQ[3:0] I/O
Data input/output: Bidirectional data bus for the x4 configuration.
DQ[7:0] I/O
Data input/output: Bidirectional data bus for the x8 configuration.
DQS#, DQS I/O
Data strobe: Output with read data. Edge-aligned with read data. Input with write data.
Center-aligned with write data. DQS# is used only when differential data strobe mode is
enabled via the LOAD MODE command.
RDQS,
RDQS#
I/O
Redundant data strobe: For the x8 configuration only. RDQS is enabled/disabled via the
LOAD MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS is
output with read data only and is ignored during write data. When RDQS is disabled, B3
becomes data mask (see DM ball). RDQS# is only used when both RDQS and the differential
data strobe mode are enabled.
V
DD
Supply
Power supply: 1.8V ±0.1V.
V
DDL
Supply
DLL power supply: 1.8V ±0.1V.
V
DDQ
Supply
DQ power supply: 1.8V ±0.1V. Isolated on the device for improved noise immunity.
V
REF
Supply
Reference voltage: V
DD
/2.
V
SS
Supply
Ground.
V
SSDL
Supply
DLL ground: Isolated on the device from Vss and Vssq.
V
SSQ
Supply
DQ ground: Isolated on the device for improved noise immunity.
NF –
No function: These balls provide no functionality on the x4 configuration only.
NU –
Not used: For the x8 configuration only. If EMR(E10) = 0, A2 is RDQS# and A8 is DQS#. If
EMR(E10) = 1, then A2 and A8 are not used.
RFU –
Reserved for future use: Row address bits A14 and A15.
