IDD Specifications
Table 9: DDR2 I
DD
Specifications and Conditions (Die Revision G) – 512MB
Values shown for MT47H64M16 DDR2 SDRAM only and are computed from values specified in the 1Gb (64 Meg x 16) com-
ponent data sheet
Parameter Symbol -1GA
-80E/
-800 -667 Units
Operating one bank active-precharge current:
t
CK =
t
CK (I
DD
),
t
RC
=
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
); CKE is HIGH, S# is HIGH between val-
id commands; Address bus inputs are switching; Data bus inputs are
switching
I
DD0
720 600 540 mA
Operating one bank active-read-precharge current: I
OUT
= 0mA;
BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS
MIN (I
DD
),
t
RCD =
t
RCD (I
DD
); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data pattern is same as
I
DD4W
I
DD1
840 700 520 mA
Precharge power-down current: All device banks idle;
t
CK =
t
CK
(I
DD
); CKE is LOW; Other control and address bus inputs are stable; Data
bus inputs are floating
I
DD2P
28 28 28 mA
Precharge quiet standby current: All device banks idle;
t
CK =
t
CK
(I
DD
); CKE is HIGH, S# is HIGH; Other control and address bus inputs are
stable; Data bus inputs are floating
I
DD2Q
360 300 260 mA
Precharge standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE
is HIGH, S# is HIGH; Other control and address bus inputs are switching;
Data bus inputs are switching
I
DD2N
380 320 280 mA
Active power-down current: All device banks open;
t
CK =
t
CK (I
DD
); CKE is LOW; Other control and address
bus inputs are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
I
DD3P
200 160 120 mA
Slow PDN exit
MR[12] = 1
40 40 40
Active standby current: All device banks open;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid
commands; Other control and address bus inputs are switching; Data
bus inputs are switching
I
DD3N
380 340 300 mA
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS
MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus inputs are switching
I
DD4W
1620 1260 800 mA
Operating burst read current: All device banks open; Continuous
burst read, I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data bus inputs are
switching
I
DD4R
1680 1280 880 mA
Burst refresh current:
t
CK =
t
CK (I
DD
); REFRESH command at every
t
RFC (I
DD
) interval; CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs
are switching
I
DD5
1200 1120 1080 mA
512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications
PDF: 09005aef83bfd5e4
htf4c64_128x64az.pdf - Rev. D 4/14 EN
10
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