© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 10
1 Publication Order Number:
MC14066B/D
MC14066B
Quad Analog Switch/Quad
Multiplexer
The MC14066B consists of four independent switches capable of
controlling either digital or analog signals. This quad bilateral switch
is useful in signal gating, chopper, modulator, demodulator and
CMOS logic implementation.
The MC14066B is designed to be pin−for−pin compatible with the
MC14016B, but has much lower ON resistance. Input voltage swings
as large as the full supply voltage can be controlled via each
independent control input.
Features
• Triple Diode Protection on All Control Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Linearized Transfer Characteristics
• Low Noise − 12 nV/√Cycle, f ≥ 1.0 kHz typical
• Pin−for−Pin Replacement for CD4016, CD4016, MC14016B
• For Lower R
ON
, Use The HC4066 High−Speed CMOS Device
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to V
SS
)
Symbol
Parameter Value Unit
V
DD
DC Supply Voltage Range −0.5 to +18.0 V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
−0.5 to V
DD
+ 0.5 V
I
in
Input Current (DC or Transient)
per Control Pin
±10 mA
I
SW
Switch Through Current ±25 mA
P
D
Power Dissipation, per Package
(Note 1)
500 mW
T
A
Ambient Temperature Range −55 to +125 °C
T
stg
Storage Temperature Range −65 to +150 °C
T
L
Lead Temperature
(8−Second Soldering)
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/C From 65C To 125C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
≤ (V
in
or V
out
) ≤ V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
http://onsemi.com
MARKING DIAGRAMS
SOIC−14
TSSOP−14
1
14
14066BG
AWLYWW
14
066B
ALYW
1
14
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or = Pb−Free Package
SOEIAJ−14
1
14
MC14066B
ALYWG
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
SOIC−14
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
SOEIAJ−14
F SUFFIX
CASE 965
PIN ASSIGNMENT
11
12
13
14
8
9
105
4
3
2
1
7
6
OUT 4
IN 4
CONTROL 4
CONTROL 1
V
DD
IN 3
OUT 3
IN 2
OUT 2
OUT 1
IN 1
V
SS
CONTROL 3
CONTROL 2
