LTC2936
22
2936fa
For more information www.linear.com/LTC2936
applicaTions inForMaTion
Manual Reset
When a GPI
n
pin is configured as MR, the in-
put is active low. If GPI
n
_MR_RESPONSE = 1,
the HISTORY_WORD register is cleared when
MR is pulled
low. An internal 15µA current source pulls MR to V
DD33
.
The MR
input can also be mapped to a GPIO pin and com-
bined with COMP
n
_HI and COMP
n
_LO faults to generate
a system reset signal.
UV Disable
When a GPI
n
pin is configured as UVDIS, the input is
active low. When UVDIS is grounded, the LTC2936 does
not respond to UV type faults. This feature is useful when
power cycling the monitored supply. An internal 15µA
current source pulls UVDIS to V
DD33
.
Margin
When a GPI
n
pin is configured as MARG, the input is
active low. When MARG is grounded, the LTC2936 does
not respond to any OV or UV faults. This feature is useful
when margining the monitored supply. An internal 15µA
current source pulls MARG to V
DD33
.
Outputs
The GPIO
n
and CMP
n
outputs are open-drain, with an
internal 15µA current source pulling to V
DD33
(optional
on the GPIOn outputs) and can tolerate a pull-up voltage
up to 14V.
All faults, GPI
n,
or other GPIO
n
inputs mapped to a GPIOn
output are combined with a logical OR function.
The GPIO
n
pins have programmable delay-on-release
timing. The GPIO
n
pin asserts its active state immediately
and de-asserts after the delay-on-release time has elapsed.
Any fault causing a GPIO
n
pin to assert while its delay-on-
release timer is active will reset the delay-on-release timer.
When a GPIO
n
indicates an alert, the alert may be cleared
using the standard SMBus Alert Response Address (ARA)
protocol. Alerts may also be cleared by reading (or clear
-
ing) HISTORY_WORD unless the condition causing the
alert persists.
The CMPn outputs can be configured as non-latching
(default) or latching. Latched CMPn outputs can be reset
by asserting MR low or by issuing a CLEAR_HISTORY
command. The CMPn outputs are active low.
Write Protect Features
When the WRITE_LOCK bit is set high, or a GPIn pin
configured as WP is pulled low, all I
2
C write word com-
mands are ignored. This feature protects against accidental
writing. The lock bit may still be written when the device
is write-protected if the provided value for KEY matches
the value in memory
.
EEPROM
The user may save and restore configuration data to the
operating memory registers at any time with STORE_USER
and RESTORE_USER commands. Upon power-up, user-
stored data is automatically loaded into the operating
memory. The part ignores I
2
C commands while performing
EEPROM transactions.
Nondestructive operation above T
A
= 85°C is possible,
but may result in a slight degradation of the retention
characteristics. The degradation in EEPROM retention
for temperatures exceeding 85°C can be approximated
by calculating the acceleration factor:
AF = e
E
a
k
⎛
⎝
⎜
⎞
⎠
⎟
•
1
T
USE
+273
−
1
T
STRESS
+273
⎛
⎝
⎜
⎞
⎠
⎟
⎡
⎣
⎢
⎤
⎦
⎥
where:
AF = acceleration factor
E
a
= activation energy = 1.5eV
k = 8.617 • 10
–5
eV/°K
T
USE
= 85°C maximum specified junction temperature
T
STRESS
= actual junction temperature °C
Example: calculate effect on retention when operating at
a junction temperature of 95°C for 10 hours.
T
STRESS
= 95°C, T
USE
= 85°C, AF = 3.74
So the overall retention of the EEPROM was degraded
by 37.4 hours as a result of operation at a junction tem
-
perature of 95°C for 10 hours. Note that the effect of this
overstress is negligible when compared to the overall
EEPROM retention rating of 10 years (87,600 hours) at a
temperature of 85°C.
