10
LT1363
Input Considerations
Each of the LT1363 inputs is the base of an NPN and a PNP
transistor whose base currents are of opposite polarity
and provide first-order bias current cancellation. Because
of variation in the matching of NPN and PNP beta, the
polarity of the input bias current can be positive or nega-
tive. The offset current does not depend on NPN/PNP beta
matching and is well controlled. The use of balanced
source resistance at each input is recommended for
applications where DC accuracy must be maximized.
The inputs can withstand transient differential input volt-
ages up to 10V without damage and need no clamping or
source resistance for protection. Differential inputs, how-
ever, generate large supply currents (tens of mA) as
required for high slew rates. If the device is used with
sustained differential inputs, the average supply current
will increase, excessive power dissipation will result and
the part may be damaged. The part should not be used as
a comparator, peak detector or other open-loop applica-
tion with large, sustained differential inputs. Under
normal, closed-loop operation, an increase of power dis-
sipation is only noticeable in applications with large slewing
outputs and is proportional to the magnitude of the
differential input voltage and the percent of the time that
the inputs are apart. Measure the average supply current
for the application in order to calculate the power dissipa-
tion.
Single Supply Operation
The LT1363 is specified at ±15V, ±5V, and ±2.5V supplies,
but it is also well suited to single supply operation down
to a single 5V supply. The symmetrical input Ccmmon
mode range and output swing make the device well suited
for applications with a single supply if the the input and
output swing ranges are centered (i.e., a DC bias of 2.5V
on the input and the output). For 5V video applications
with an assymetrical swing, an offset of 2V on the input
works best.
Power Dissipation
The LT1363 combines high speed and large output drive
in a small package. Because of the wide supply voltage
range, it is possible to exceed the maximum junction
APPLICATIONS INFORMATION
WUU
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temperature under certain conditions. Maximum junction
temperature (T
J
) is calculated from the ambient tempera-
ture (T
A
) and power dissipation (P
D
) as follows:
LT1363CN8: T
J
= T
A
+ (P
D
x 130°C/W)
LT1363CS8: T
J
= T
A
+ (P
D
x 190°C/W)
Worst case power dissipation occurs at the maximum
supply current and when the output voltage is at 1/2 of
either supply voltage (or the maximum swing if less than
1/2 supply voltage). Therefore P
DMAX
is:
P
DMAX
= (V
+
– V
–
)(I
SMAX
) + (V
+
/2)
2
/R
L
Example: LT1363CS8 at 70°C, V
S
= ±15V, R
L
= 390Ω
P
DMAX
= (30V)(8.7mA) + (7.5V)
2
/390Ω = 405mW
T
JMAX
= 70°C + (405mW)(190°C/W) = 147°C
Circuit Operation
The LT1363 circuit topology is a true voltage feedback
amplifier that has the slewing behavior of a current feed-
back amplifier. The operation of the circuit can be under-
stood by referring to the simplified schematic. The inputs
are buffered by complementary NPN and PNP emitter
followers which drive a 500Ω resistor. The input voltage
appears across the resistor generating currents which are
mirrored into the high impedance node. Complementary
followers form an output stage which buffers the gain
node from the load. The bandwidth is set by the input
resistor and the capacitance on the high impedance node.
The slew rate is determined by the current available to
charge the gain node capacitance. This current is the
differential input voltage divided by R1, so the slew rate is
proportional to the input. Highest slew rates are therefore
seen in the lowest gain configurations. For example, a 10V
output step in a gain of 10 has only a 1V input step,
whereas the same output step in unity gain has a 10 times
greater input step. The curve of Slew Rate vs Input Level
illustrates this relationship. The LT1363 is tested for slew
rate in a gain of –2 so higher slew rates can be expected
in gains of 1 and –1, and lower slew rates in higher gain
configurations.
