AD1851RZ-REEL7 Datasheet AD1851RZ-REEL7, AD1851RZ, AD1851RZ-J | P4-P6

AD1851/AD1861

REV. A

–4–

ABSOLUTE MAXIMUM RATINGS*

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.50 V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.50 V

–V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –6.50 V to 0 V

Digital Inputs to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V

Short Circuit . . . . . . . . . . . . . . . . .Indefinite Short to Ground

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+300°C, 10 sec

Storage Temperature . . . . . . . . . . . . . . . . . . –60°C to +100°C

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the

operational section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

PIN DESCRIPTIONS

1–V

Analog Negative Power Supply

2 DGND Logic Ground

Logic Positive Power Supply

4 NC No Connection

5 CLK Clock Input

6 LE Latch Enable Input

7 DATA Serial Data Input

8 NC No Internal Connection*

OUT

Voltage Output

10 R

Feedback Resistor

11 SJ Summing Junction

12 AGND Analog Ground

13 I

OUT

Current Output

14 MSB ADJ MSB Adjustment Terminal

15 TRIM MSB Trimming Potentiometer Terminal

16 V

Analog Positive Power Supply

*Pin 8 has no internal connection; -V

from AD1856 or AD1860 socket can be

safely applied.

ORDERING GUIDE

Package

Model Resolution THD + N Option*

AD1851N 16 Bits 0.008% N-16

AD1851N-J 16 Bits 0.004% N-16

AD1851R 16 Bits 0.008% R-16

AD1851R-J 16 Bits 0.004% R-16

AD1861N 18 Bits 0.008% N-16

AD1861N-J 18 Bits 0.004% N-16

AD1861R 18 Bits 0.008% R-16

AD1861R-J 18 Bits 0.004% R-16

*N = Plastic DIP Package; R = Small Outline (SOIC) Package.

CAUTION

ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;

however, permanent damage may occur on unconnected devices subject to high energy electro-

static fields. Unused devices must be stored in conductive foam or shunts. The protective foam

should be discharged to the destination socket before devices are inserted.

WARNING!

ESD SENSITIVE DEVICE

Typical Performance

175

150

125

100

2 4 6 8 10 12 14

CLOCK FREQUENCY – MHz

PD – mW

Power Dissipation vs. Clock Frequency

THD+N – %

0.1

0.01

0.001

–30 –20 –10 0 10 20 30 40 50 60 70 80 90

TEMPERATURE –

–60dB

–20dB

0dB

THD vs. Temperature

AD1851/AD1861

REV. A

–5–

TOTAL HARMONIC DISTORTION

Total harmonic distortion plus noise (THD+N) is defined as

the ratio of the square root of the sum of the squares of the val-

ues of the first 19 harmonics and noise to the value of the funda-

mental input frequency. It is usually expressed in percent (%).

THD+N is a measure of the magnitude and distribution of lin-

earity error, differential linearity error, quantization error and

noise. The distribution of these errors may be different, depend-

ing on the amplitude of the output signal. Therefore, to be most

useful, THD+N should be specified for both large (0 dB) and

small signal amplitudes (–20 dB and –60 dB).

The THD+N figure of an audio DAC represents the amount of

undesirable signal produced during reconstruction and playback

of an audio waveform. This specification, therefore, provides a

direct method to classify and choose an audio DAC for a

desired level of performance.

SETTLING TIME

Settling time is the time required for the output of the DAC to

reach and remain within a specified error band about its final

value, measured from the digital input transition. It is a primary

measure of dynamic performance.

MIDSCALE ERROR

Midscale error, or bipolar zero error, is the deviation of the ac-

tual analog output from the ideal output (0 V) when the 2s

complement input code representing half scale is loaded in the

input register.

D-RANGE DISTORTION

D-range distortion is equal to the value of the total harmonic

distortion + noise (THD+N) plus 60 dB when a signal level of

–60 dB below full scale is reproduced. D-range is tested with a

1 kHz input sine wave. This is measured with a standard A-

weight filter as specified by EIAJ Standard CP-307.

SIGNAL-TO-NOISE RATIO

The signal-to-noise ratio (SNR) is defined as the ratio of the

amplitude of the output when a full-scale output is present to

the amplitude of the output with no signal present. This is mea-

sured with a standard A-weight filter as specified by EIAJ

Standard CP-307.

REFERENCE

OUT

DAC

AUDIO

OUTPUT

INPUT LATCH

DATALECLOCK

SERIAL-TO-PARALLEL

CONVERSION

Figure 1. AD1851/AD1861 Functional Block Diagram

FUNCTIONAL DESCRIPTION

The AD1851/AD1861 is a complete monolithic PCM audio

DAC. No additional external components are required for op-

eration. As shown in Figure 1 above, each chip contains a volt-

age reference, an output amplifier, a DAC, an input latch and a

parallel input register.

The voltage reference consists of a bandgap circuit and buffer

amplifier. This combination of elements produces a reference

voltage that is unaffected by changes in temperature and age.

The DAC output voltage, which is derived from the reference

voltage, is also unaffected by these environmental changes.

The output amplifier uses both MOS and bipolar devices to

produce low offset, high slew rate and optimum settling time.

When combined with the on-chip feedback resistor, the output

op amp converts the output current of the AD1851/AD1861 to

a voltage output.

The DAC uses a combination of segmented decoder and R-2R

architecture to achieve consistent linearity and differential lin-

earity. The resistors which form the ladder structure are fabri-

cated with silicon chromium thin film. Laser-trimming of these

resistors further reduces linearity error, resulting in low output

distortion.

The input register and serial-to-parallel converter are fabricated

with CMOS logic gates. These gates allow the achievement of

fast switching speeds and low power consumption. This contrib-

utes to the overall low power dissipation of the AD1851/

AD1861.

AD1851/AD1861

REV. A

–6–

Analog Circuit Considerations

GROUNDING RECOMMENDATIONS

The AD1851/AD1861 has two ground pins, designated Analog

and Digital ground. The analog ground pin is the “high quality”

ground reference point for the device. The analog ground pin

should be connected to the analog common point in the system.

The output load should also be connected to that same point.

The digital ground pin returns ground current from the digital

logic portions of the AD1851/AD1861 circuitry. This pin

should be connected to the digital common point in the system.

As illustrated in Figure 2, the analog and digital grounds should

be connected together at one point in the system.

DGND AGND

AD1851/AD1861

–

ANALOG

GROUND

DIGITAL

GROUND

3 16

12 12

+5V

–V

Figure 2. Recommended Circuit Schematic

POWER SUPPLIES AND DECOUPLING

The AD1851/AD1861 has three power supply input pins. The

±V

supplies provide the supply voltages to operate the linear

portions of the DAC including the voltage reference, output am-

plifier and control amplifier. The ±V

supplies are designed to

operate at ±5 V.

The +V

supply operates the digital portions of the chip includ-

ing the input shift register and the input latching circuitry. The

supply is designed to operate at +5 V.

Decoupling capacitors should be used on all power supply pins.

Furthermore, good engineering practice suggests that these ca-

pacitors be placed as close as possible to the package pins as

well as to the common points. The logic supply, +V

, should be

decoupled to digital common, while the analog supplies, ±V

should be decoupled to analog common.

The use of three separate power supplies will reduce feedthrough

from the digital portion of the system to the linear portion of the

system, thus contributing to improved performance.

However, three separate voltage supplies are not necessary for

good circuit performance. For example, Figure 3 illustrates a

system where only a single positive and a single negative supply

are available.

In this example, the positive logic and positive analog supplies

must both be connected to +5 V, while the negative analog sup-

ply will be connected to –5 V. Performance would benefit from

a measure of isolation between the supplies introduced by using

simple low pass filters in the individual power supply leads.

DGND AGND

AD1851/AD1861

ANALOG

GROUND

DIGITAL

GROUND

–V

–5V

+5V

Figure 3. Alternate Recommended Schematic

As with most linear circuits, changes in the power supplies will

affect the output of the DAC. Analog Devices recommends that

well regulated power supplies with less than 1% ripple be incor-

porated into the design of any system using the AD1851/AD1861.

OPTIONAL MSB ADJUSTMENT

Use of an optional adjustment circuit allows residual differential

linearity error around midscale to be eliminated. This error is

especially important when low amplitude signals are being re-

produced. In those cases, as the signal amplitude decreases, the

ratio of the midscale differential linearity error to the signal am-

plitude increases, thereby increasing THD.

Therefore, for best performance at low output levels, the op-

tional MSB adjust circuitry shown in Figure 4 may be used to

improve performance. The adjustment should be made with a

small signal input (–20 dB or –60 dB).

TRIM

470kΩ 100kΩ 200kΩ

MSB

ADJUST

–V

Figure 4. Optional THD Adjust Circuit

P1-P3 P4-P6 P7-P9 P10-P12

AD1851RZ-REEL7

Mfr. #:

Buy AD1851RZ-REEL7

Manufacturer:

Analog Devices Inc.

Description:

Audio D/A Converter ICs IC MONO 16-BIT AUDIO

Lifecycle:

New from this manufacturer.

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AD1851RZ-REEL7

AD1851RZ-REEL7

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