74AHC_AHCT374_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 12 June 2008 3 of 17
NXP Semiconductors
74AHC374; 74AHCT374
Octal D-type flip-flop; positive edge-trigger; 3-state
Fig 2. Logic symbol Fig 3. IEC logic symbol
mna891
D0
D1
D2
D3
D4
D5
D6
D7
OE
CP
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
11
1
19
16
15
12
9
6
5
2
18
17
14
13
8
7
4
3
mna196
19
16
15
12
9
6
5
11
C1
1
EN
1D
2
18
17
14
13
8
7
4
3
Fig 4. Logic diagram
mna893
Q4
D4
Q3
D3
Q2
D2
Q1
D1
Q0
D0
D
FF1
Q
CP
CP
D
FF2
Q
CP
D
FF3
Q
CP
D
FF4
Q
CP
D
FF5
Q
CP
D
FF6
Q
CP
D
FF7
Q
CP
D
FF8
Q
CP
OE
Q5
D5
Q6
D6
Q7
D7
74AHC_AHCT374_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 12 June 2008 4 of 17
NXP Semiconductors
74AHC374; 74AHCT374
Octal D-type flip-flop; positive edge-trigger; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 5. Pin configuration SO20 and TSSOP20
374
OE V
CC
Q0 Q7
D0 D7
D1 D6
Q1 Q6
Q2 Q5
D2 D5
D3 D4
Q3 Q4
GND CP
001aad040
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
Table 2. Pin description
Symbol Pin Description
OE 1 3-state output enable input (active LOW)
Q0 2 3-state flip-flop output
D0 3 data input
D1 4 data input
Q1 5 3-state flip-flop output
Q2 6 3-state flip-flop output
D2 7 data input
D3 8 data input
Q3 9 3-state flip-flop output
GND 10 ground (0 V)
CP 11 clock input (LOW-to-HIGH, edge triggered)
Q4 12 3-state flip-flop output
D4 13 data input
D5 14 data input
Q5 15 3-state flip-flop output
Q6 16 3-state flip-flop output
D6 17 data input
D7 18 data input
Q7 19 3-state flip-flop output
V
CC
20 supply voltage
74AHC_AHCT374_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 12 June 2008 5 of 17
NXP Semiconductors
74AHC374; 74AHCT374
Octal D-type flip-flop; positive edge-trigger; 3-state
6. Functional description
[1] H = HIGH voltage level;
h = HIGH voltage level one setup time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one setup time prior to the LOW-to-HIGH CP transition;
X = don’t care;
= LOW-to-HIGH CP transition;
Z = high-impedance OFF-state.
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO20 packages: above 70 °C the value of P
tot
derates linearly at 8 mW/K.
For TSSOP20 packages: above 60 °C the value of P
tot
derates linearly at 5.5 mW/K.
Table 3. Function table
[1]
Operating mode Control Input Internal
flip-flop
Output
OE CP Dn Q0 to Q7
Load and read register L lL L
L hH H
Load register and disable outputs H lL Z
H hH Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +7.0 V
V
I
input voltage 0.5 +7.0 V
I
IK
input clamping current V
I
< 0.5 V
[1]
20 - mA
I
OK
output clamping current V
O
< 0.5 V or V
O
> V
CC
+ 0.5 V
[1]
20 +20 mA
I
O
output current V
O
= 0.5 V to (V
CC
+ 0.5 V) 25 +25 mA
I
CC
supply current - +75 mA
I
GND
ground current 75 - mA
T
stg
storage temperature 65 +150 °C
P
tot
total power dissipation T
amb
= 40 °C to +125 °C
[2]
- 500 mW

74AHC374PW,112

Mfr. #:
Manufacturer:
Nexperia
Description:
Flip Flops OCTAL D FLIP FLOP
Lifecycle:
New from this manufacturer.
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