IDT
®
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 1586P - 11/19/15
9ZX21901B
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
17
Ordering Information
Part / Order Number Shipping Package Package Temperature
9ZX21901BKLF Trays 72-pin MLF 0 to +70°C
9ZX21901BKLFT Tape and Reel 72-pin MLF 0 to +70°C
"LF" designates PB-free configuration, RoHS compliant.
Revision History
Rev. Issue Date Who Description Page #
A 5/13/2009 RDW
1. Slightly modified name of pin 6 and corrected pin description of pin 6, to remove
reference to CK505
2. Added Typical numbers to key parameters in electrical characteristics tables.
3. Move to final.
Various
B 8/7/2009 RDW
1. Updated Pin 8 name to VDDR to indicate that it is the VDD for the input receiver.
2. Chan
e MAX operatin
current from 600 to 500mA.
Various
C 8/12/2009 RDW 1. Updated VDDR pin description to include 3.3V information. Various
D 8/14/2009 RDW 1. Inserted Pins 19 and 72 into pinout after they were inadvertenly removed. 2
E 10/7/2009 RDW 1. Corrected units from ns to ps for the tDSPO_PLL and tDSPO_BYP parameters
F 6/22/2010 RDW
1. Updated QPI reference to 9.6GTs, added note about variable feedback path
2. Reformatted electrical tables to fit new standard format
3. Merged Phase Jitter Tables into Single Table.
4. Added output termination/test load drawin
and table 1, 5, 6, 9
G 8/3/2010 RDW
1. Updated front page to standard 9ZX format.
2. Clarified that SMBus Address Selection table includes the Read/Write Bit. Minor
clarifications to other tables.
3. Added additive phase jitter table for bypass mode. 1-3, 5-11
H 3/2/2011 RDW 1. Added rise/fall varation spec to HCSL_Out table 6
J 12/8/2011 RDW 1. Updated tDSPO_BYP parameter from +/-350 to +/-250ps. 7
K 4/12/2012 RDW
1. Updated Rp values on Output Terminations Table from 43.2 ohms to 42.2 or 43.2 ohms
to be consistent with Intel.
9
L 12/17/2012 RG
1. Updated Abs Max table to include Case Temperature at 110 °C max.
2. Added Thermal Characteristics table
5, 9
M 4/15/2013 RDW
1. Corrected typo in OE# Latency parameter; changed 1 min. to 3 max. cycles to 4 min. to
12 max. clocks.
5
N 1/7/2015 DC Updated package drawing and dimensions from PUNCH to SAWN Various
P 11/19/2015 RDW Update Input Clock spec with new standardized table matching PCIe SIG input specs. 5
