74ABT125CSJX Datasheet 74ABT125CSC, 74ABT125CSJX, 74ABT125CMTC | P1-P3

74ABT125 — Quad Buffer with 3-STATE Outputs

74ABT125 Rev. 1.4.0

January 2008

74ABT125

Quad Buffer with 3-STATE Outputs

Features

■

Non-inverting buffers

■

Output sink capability of 64mA, source capability of

32mA

■

Guaranteed latchup protection

■

High impedance glitch free bus loading during entire

power up and power down cycle

■

Nondestructive hot insertion capability

■

Disable time less than enable time to avoid bus

contention

General Description

The ABT125 contains four independent non-inverting

buffers with 3-STATE outputs.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Connection Diagram

Pin Description

Function Table

H

=

HIGH Voltage Level

L

=

LOW Voltage Level

Z

=

HIGH Impedance

X

=

Immaterial

Order Number

Package

Number Package Description

74ABT125CSC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"

Narrow

74ABT125CSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74ABT125CMTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

Pin Names Description

A

n

, B

n

Inputs

O

n

Outputs

Inputs Output

A

n

B

n

O

n

L L L

L H H

H X Z

74ABT125 Rev. 1.4.0 2

74ABT125 — Quad Buffer with 3-STATE Outputs

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Note:

1. Either voltage limit or current limit is sufficient to protect inputs.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to absolute maximum ratings.

Symbol Parameter Rating

T

STG

Storage Temperature –65°C to +150°C

T

A

Ambient Temperature Under Bias –55°C to +125°C

T

J

Junction Temperature Under Bias –55°C to +150°C

V

CC

V

CC

Pin Potential to Ground Pin –0.5V to +7.0V

V

IN

Input Voltage

(1)

–0.5V to +7.0V

I

IN

Input Current

(1)

–30mA to +5.0mA

V

O

Voltage Applied to Any Output

Disabled or Power-Off State –0.5V to 5.5V

HIGH State –0.5V to V

CC

Current Applied to Output in LOW State (Max.) twice the rated I

OL

(mA)

DC Latchup Source Current (Across Comm Operating Range) –300mA

Over Voltage Latchup (I/O) 10V

Symbol Parameter Rating

T

A

Free Air Ambient Temperature –40°C to +85°C

V

CC

Supply Voltage +4.5V to +5.5V

∆

V

/

∆

t Minimum Input Edge Rate

Data Input 50mV/ns

Enable Input 20mV/ns

74ABT125 Rev. 1.4.0 3

74ABT125 — Quad Buffer with 3-STATE Outputs

DC Electrical Characteristics

Notes:

2. Guaranteed, but not tested.

3. For 8-bit toggling, I

CCD

<

0.8mA/MHz.

Symbol Parameter V

CC

Conditions Min. Typ. Max. Units

V

IH

Input HIGH Voltage Recognized HIGH Signal 2.0 V

V

IL

Input LOW Voltage Recognized LOW Signal 0.8 V

V

CD

Input Clamp Diode Voltage Min. I

IN

=

–18mA –1.2 V

V

OH

Output HIGH Voltage Min. I

OH

=

–3mA 2.5 V

I

OH

=

–32mA 2.0

V

OL

Output LOW Voltage Min. I

OL

=

64mA 0.55 V

I

IH

Input HIGH Current Max. V

IN

=

2.7V

(2)

1µA

V

IN

=

V

CC

1

I

BVI

Input HIGH Current Breakdown

Test

Max. V

IN

=

7.0V 7 µA

I

IL

Input LOW Current Max. V

IN

=

0.5V

(2)

–1 µA

V

IN

=

0.0V –1

V

ID

Input Leakage Test 0.0 I

ID

=

1.9µA, All Other Pins

Grounded

4.75 V

I

OZH

Output Leakage Current 0–5.5V V

OUT

=

2.7V, OE

n

=

2.0V 10 µA

I

OZL

Output Leakage Current 0–5.5V V

OUT

=

0.5V, OE

n

=

2.0V –10 µA

I

OS

Output Short-Circuit Current Max. V

OUT

=

0.0V –275 mA

I

CEX

Output HIGH Leakage Current Max. V

OUT

=

V

CC

50 µA

I

ZZ

Bus Drainage Test 0.0 V

OUT

=

5.5V, All Others GND 100 µA

I

CCH

Power Supply Current Max. All Outputs HIGH 50 µA

I

CCL

Power Supply Current Max. All Outputs LOW 15 mA

I

CCZ

Power Supply Current Max. OE

n

=

V

CC

, All Others at V

CC

or Ground

50 µA

I

CCT

Additional

I

CC

/Input

Outputs Enabled Max. V

I

=

V

CC

– 2.1V 1.5 mA

Outputs 3-STATE Enable Input V

I

=

V

CC

– 2.1V 1.5 mA

Outputs 3-STATE Data Input V

I

=

V

CC

– 2.1V,

All Others at V

CC

or Ground

50 µA

I

CCD

Dynamic I

CC

No Load

(2)

Max. Outputs OPEN, OE

n

=

GND

(3)

,

One-Bit Toggling,

50% Duty Cycle

0.1 mA/

MHz

74ABT125CSJX

74ABT125CSJX

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