PIC16(L)F183XX
DS40001744C-page 14 2014-2016 Microchip Technology Inc.
TABLE 7: 14/16-PIN ALLOCATION TABLE (PIC16(L)F18326)
I/O
(2)
14/16-Pin PDIP/SOIC/TSSOP
16-Pin UQFN
ADC
Reference
Comparator
NCO
DAC
DSM
Timers
CCP
PWM
CWG
MSSP
EUSART
CLC
CLKR
Interrupt
Pull-up
Basic
RA0
13 12 ANA0
—
C1IN0+
—
DAC1OUT
— — — — —
SS2
(1)
— —
—
IOCA0
Y ICDDAT/
ICSPDAT
RA1 12 11 ANA1 VREF
+
C1IN0-
C2IN0-
—DAC1REF+— — — — — — — — —IOCA1 Y ICDCLK/
ICSPCLK
RA2 11 10 ANA2 VREF- — — DAC1REF- — T0CKI
(1)
CCP3
(1)
— CWG1
(1)
CWG2
(1)
—
— — — INT
(1)
IOCA2
Y —
RA3 4 3 — — —— — — —— — — ————IOCA3 Y MCLR
VPP
RA4 3 2 ANA4
— — — — —
T1G
(1)
SOSCO
— — — — — — —
IOCA4 Y CLKOUT
OSC2
RA5 2 1 ANA5 — —— — —T1CKI
(1)
SOSCIN
SOSCI
—— ———
CLCIN3
(1)
— IOCA5 Y CLKIN
OSC1
RC0 10 9 ANC0 — C2IN0+
— — — T5CKI
(1)
— — — SCK1
(1)
SCL1
(1,3,4)
— — —
IOCC0 Y —
RC1 9 8 ANC1 — C1IN1-
C2IN1-
— — — — CCP4
(1)
——SDI1
(1)
SDA1
(1,3,4)
— CLCIN2
(1)
— IOCC1 Y —
RC2 8 7 ANC2 — C1IN2-
C2IN2-
— — MDCIN1
(1)
— — — — — — — —
IOCC2 Y —
RC3 7 6 ANC3 — C1IN3-
C2IN3-
——MDMIN
(1)
T5G
(1)
CCP2
(1)
——SS1
(1)
— CLCIN0
(1)
— IOCC3 Y —
RC4 6 5
ANC4 — — — — —
T3G
(1)
— — — SCK2
(1)
SCL2
(1,3,4)
TX
(1)
CK
(1)
CLCIN1
(1)
— IOCC4 Y —
RC5 5 4 ANC5 — — — — MDCIN2
(1)
T3CKI
(1)
CCP1
(1)
——SDI2
(1)
SDA2
(1,3,4)
RX
(1)
DT
(1,3
)
——IOCC5 Y —
VDD 1 16
— — — — — — — — — — — — — — — —
VDD
VSS 14 13 — — — — — — — — — — — — — — — — VSS
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
4: These pins are configured for I
2
C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.